| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2-diagnostic.txt | 24 # tbh [r0, sp, lsl #1]
29 # tbh [r0, pc, lsl #1]
34 # tbh [sp, r0, lsl #1]
39 # tbh [pc, r0, lsl #1]
46 # CHECK: tbh [r0, sp, lsl #1]
47 # CHECK: tbh [r0, pc, lsl #1]
48 # CHECK: tbh [sp, r0, lsl #1]
49 # CHECK: tbh [pc, r0, lsl #1]
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| D | thumb-tests.txt | 176 # CHECK: tbh [r5, r4, lsl #1]
|
| /external/scapy/scapy/layers/tls/crypto/ |
| D | prf.py | 299 tbh = key + client_random + server_random
301 tbh = key + server_random + client_random
302 export_key = _tls_hash_algs["MD5"]().digest(tbh)[:req_len]
328 tbh = client_random + server_random
330 tbh = server_random + client_random
331 iv = _tls_hash_algs["MD5"]().digest(tbh)[:req_len]
|
| /external/llvm/lib/Target/ARM/ |
| D | README-Thumb2.txt | 6 of tbb / tbh.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | README-Thumb2.txt | 6 of tbb / tbh.
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | README-Thumb2.txt | 6 of tbb / tbh.
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-jtb.ll | 3 ; Do not use tbb / tbh if any destination is before the jumptable.
9 ; CHECK-NOT: tbh
|
| D | constant-islands-jump-table.ll | 5 ; CHECK-NOT: tbh
|
| D | thumb2-tbh.ll | 3 ; Thumb2 target should reorder the bb's in order to use tbb / tbh.
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-jtb.ll | 4 ; Do not use tbb / tbh if any destination is before the jumptable.
10 ; CHECK-NOT: tbh
|
| D | constant-islands-jump-table.ll | 5 ; CHECK-NOT: tbh
|
| D | thumb2-tbh.ll | 10 ; Thumb2 target should reorder the bb's in order to use tbb / tbh.
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | jump-table-tbh.ll | 12 ; T2: tbh [pc, r{{[0-9]+}}, lsl #1]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-diagnostics.s | 180 tbh [r0, sp, lsl #1]
183 tbh [r0, pc, lsl #1]
186 tbh [sp, r0, lsl #1]
|
| D | basic-thumb2-instructions.s | 3503 tbh [r3, r8, lsl #1]
3510 @ CHECK: tbh [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-tests.txt | 173 # CHECK: tbh [r5, r4, lsl #1]
|
| D | thumb2.txt | 2268 # CHECK: tbh [r3, r8, lsl #1]
|
| /external/capstone/suite/cstest/ |
| D | issues.cs | 15 0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0…
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 378 tbh [r0, r1, LSL #1] label
807 # CHECK-NEXT: 2 2 0.50 U tbh [r0, r1, lsl #1]
1247 … - 0.50 0.50 - - - - - - - - tbh [r0, r1, lsl #1]
|
| D | m4-int.s | 387 tbh [r0, r1, LSL #1] label
831 # CHECK-NEXT: 1 1 1.00 U tbh [r0, r1, lsl #1]
1269 # CHECK-NEXT: 1.00 tbh [r0, r1, lsl #1]
|
| D | cortex-a57-thumb.s | 765 tbh [r3, r8, lsl #1]
1672 # CHECK-NEXT: 2 3 1.00 U tbh [r3, r8, lsl #1]
2586 # CHECK-NEXT: 1.00 0.50 0.50 - - - - - tbh [r3, r8, lsl #1]
|
| /external/capstone/ |
| D | ChangeLog | 19 - Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back agai…
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3597 void tbh(Condition cond, Register rn, Register rm);
3598 void tbh(Register rn, Register rm) { tbh(al, rn, rm); } in tbh() function
|
| D | disasm-aarch32.h | 1351 void tbh(Condition cond, Register rn, Register rm);
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3244 tbh [r3, r8, lsl #1]
3251 @ CHECK: tbh [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0]
|