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Searched refs:tbnz (Results 1 – 25 of 65) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
Dtbz-tbnz.ll13 ; CHECK: tbnz [[CMP]], #31
31 ; CHECK: tbnz [[CMP]], #63
49 ; CHECK: tbnz [[CMP]], #31
67 ; CHECK: tbnz [[CMP]], #63
85 ; CHECK: tbnz [[CMP]], #31
103 ; CHECK: tbnz [[CMP]], #63
121 ; CHECK: tbnz [[CMP]], #31
147 ; CHECK: tbnz [[CMP]], #63
181 ; CHECK: tbnz x0, #63
197 ; CHECK: tbnz x0, #63
[all …]
Dfast-isel-tbz.ll66 ; CHECK: tbnz w0, #0, {{LBB.+_2}}
78 ; CHECK: tbnz w0, #1, {{LBB.+_2}}
90 ; CHECK: tbnz w0, #2, {{LBB.+_2}}
102 ; CHECK: tbnz w0, #3, {{LBB.+_2}}
114 ; CHECK: tbnz x0, #32, {{LBB.+_2}}
126 ; FAST: tbnz w0, #7, {{LBB.+_2}}
137 ; FAST: tbnz w0, #15, {{LBB.+_2}}
148 ; CHECK: tbnz w0, #31, {{LBB.+_2}}
159 ; CHECK: tbnz x0, #63, {{LBB.+_2}}
192 ; FAST: tbnz w0, #7, {{LBB.+_2}}
[all …]
Dcheck-sign-bit-before-extension.ll13 ; CHECK: tbnz w0, #7, .LBB
30 ; CHECK: tbnz w0, #15, .LBB
47 ; CHECK: tbnz w0, #31, .LBB
64 ; CHECK: tbnz w0, #7, .LBB
81 ; CHECK: tbnz w0, #15, .LBB
98 ; CHECK: tbnz w0, #31, .LBB
115 ; CHECK: tbnz w0, #31, .LBB
133 ; CHECK: tbnz w0, #31, .LBB
Dand-sink.ll13 ; CHECK: tbnz {{w[0-9]+}}, #2
42 ; CHECK: tbnz {{w[0-9]+}}, #2
Dbranch-relax-asm.ll5 ; It would be more natural to use just one "tbnz %false" here, but if the
Doptimize-cond-branch.ll5 ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
/external/llvm/test/CodeGen/AArch64/
Dfast-isel-tbz.ll66 ; CHECK: tbnz w0, #0, {{LBB.+_2}}
78 ; CHECK: tbnz w0, #1, {{LBB.+_2}}
90 ; CHECK: tbnz w0, #2, {{LBB.+_2}}
102 ; CHECK: tbnz w0, #3, {{LBB.+_2}}
114 ; CHECK: tbnz x0, #32, {{LBB.+_2}}
126 ; FAST: tbnz w0, #7, {{LBB.+_2}}
137 ; FAST: tbnz w0, #15, {{LBB.+_2}}
148 ; CHECK: tbnz w0, #31, {{LBB.+_2}}
159 ; CHECK: tbnz x0, #63, {{LBB.+_2}}
192 ; FAST: tbnz w0, #7, {{LBB.+_2}}
[all …]
Dtbz-tbnz.ll49 ; CHECK: tbnz [[CMP]], #31
67 ; CHECK: tbnz [[CMP]], #63
85 ; CHECK: tbnz [[CMP]], #31
103 ; CHECK: tbnz [[CMP]], #63
147 ; CHECK: tbnz [[CMP]], #63
265 ; CHECK: tbnz w0, #0
281 ; CHECK: tbnz w0, #0
299 ; CHECK: tbnz w0, #2
317 ; CHECK: tbnz w0, #3
334 ; CHECK: tbnz w0, #31
[all …]
Doptimize-cond-branch.ll5 ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
14 ; CHECK: tbnz
Dbranch-relax-asm.ll5 ; It would be more natural to use just one "tbnz %false" here, but if the
Danalyze-branch.ll149 ; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
216 ; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
/external/llvm-project/lld/test/ELF/
Daarch64-tstbr14-reloc.s20 # CHECK-NEXT: 21013c: tbnz w3, #15, 0x210120 <_foo>
21 # CHECK-NEXT: 210140: tbnz w3, #15, 0x210130 <_bar>
60 #DSO-NEXT: 10314: tbnz w3, #15, 0x10350 <_foo@plt>
61 #DSO-NEXT: 10318: tbnz w3, #15, 0x10360 <_bar@plt>
91 tbnz w3, #15, _foo
92 tbnz w3, #15, _bar
/external/arm-trusted-firmware/drivers/arm/pl011/aarch64/
Dpl011_console.S134 tbnz w2, #PL011_UARTFR_TXFF_BIT, 1b
140 tbnz w2, #PL011_UARTFR_TXFF_BIT, 2b
182 tbnz w1, #PL011_UARTFR_RXFE_BIT, no_char
227 tbnz w1, #PL011_UARTFR_BUSY_BIT, 1b
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dopt-fold-and-tbz-tbnz.mir30 ; tbnz (and x, 8), 3 == tbnz x, 3 because the third bit of x & 8 is 1 when
101 ; tbnz (and x, 7), 3 != tbnz x, 3, because the third bit of x & 7 is always
/external/arm-trusted-firmware/drivers/amlogic/console/aarch64/
Dmeson_console.S169 tbnz w2, #MESON_STATUS_TX_FULL_BIT, 1b
175 tbnz w2, #MESON_STATUS_TX_FULL_BIT, 2b
217 tbnz w1, #MESON_STATUS_RX_EMPTY_BIT, 1f
/external/llvm/test/MC/AArch64/
Darm64-branch-encoding.s115 tbnz x1, #63, foo
120 tbnz w1, #31, foo
127 tbnz x3, #8, #-32768
128 ; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37]
Delf-reloc-tstb.s5 tbnz w3, #15, somewhere
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-branch-encoding.s115 tbnz x1, #63, foo
120 tbnz w1, #31, foo
127 tbnz x3, #8, #-32768
128 ; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37]
Delf-reloc-tstb.s8 tbnz w3, #15, somewhere
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-branch.txt20 # CHECK: tbnz w11, #3, #0
58 # CHECK: tbnz w0, #1, #12
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-branch.txt20 # CHECK: tbnz w11, #3, #0
58 # CHECK: tbnz w0, #1, #12
/external/arm-trusted-firmware/plat/imx/common/
Dimx_uart_console.S75 tbnz w1, #5, 1b
/external/arm-trusted-firmware/lib/cpus/aarch64/
Dwa_cve_2017_5715_bpiall.S336 tbnz w2, #3, bpiall_ret_serror
337 tbnz w2, #2, bpiall_ret_fiq
/external/arm-optimized-routines/string/aarch64/
D__mtag_tag_region.S38 tbnz count, 6, L(set96)
D__mtag_tag_zero_region.S38 tbnz count, 6, L(set96)

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