Searched refs:tracked_regs (Results 1 – 4 of 4) sorted by relevance
328 STATIC_ASSERT(SI_NUM_TRACKED_REGS <= sizeof(ctx->tracked_regs.reg_saved) * 8); in si_set_tracked_regs_to_clear_state()330 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000; in si_set_tracked_regs_to_clear_state()331 ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000; in si_set_tracked_regs_to_clear_state()332 ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000; in si_set_tracked_regs_to_clear_state()333 ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000; in si_set_tracked_regs_to_clear_state()334 ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff; in si_set_tracked_regs_to_clear_state()335 ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000; in si_set_tracked_regs_to_clear_state()336 ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000; in si_set_tracked_regs_to_clear_state()337 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000; in si_set_tracked_regs_to_clear_state()338 ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000; in si_set_tracked_regs_to_clear_state()[all …]
158 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 || in radeon_opt_set_context_reg_rmw()159 sctx->tracked_regs.reg_value[reg] != value) { in radeon_opt_set_context_reg_rmw()162 sctx->tracked_regs.reg_saved |= 0x1ull << reg; in radeon_opt_set_context_reg_rmw()163 sctx->tracked_regs.reg_value[reg] = value; in radeon_opt_set_context_reg_rmw()173 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 || in radeon_opt_set_context_reg()174 sctx->tracked_regs.reg_value[reg] != value) { in radeon_opt_set_context_reg()177 sctx->tracked_regs.reg_saved |= 0x1ull << reg; in radeon_opt_set_context_reg()178 sctx->tracked_regs.reg_value[reg] = value; in radeon_opt_set_context_reg()194 if (((sctx->tracked_regs.reg_saved >> reg) & 0x3) != 0x3 || in radeon_opt_set_context_reg2()195 sctx->tracked_regs.reg_value[reg] != value1 || in radeon_opt_set_context_reg2()[all …]
924 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 || in gfx10_emit_ge_pc_alloc()925 sctx->tracked_regs.reg_value[reg] != value) { in gfx10_emit_ge_pc_alloc()936 sctx->tracked_regs.reg_saved |= 0x1ull << reg; in gfx10_emit_ge_pc_alloc()937 sctx->tracked_regs.reg_value[reg] = value; in gfx10_emit_ge_pc_alloc()3363 sctx->tracked_regs.spi_ps_input_cntl, num_interp); in si_emit_spi_map()
1284 struct si_tracked_regs tracked_regs; member