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Searched refs:trn1 (Results 1 – 25 of 62) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dtrn1-diagnostics.s4 trn1 z10.h, z22.h, z31.x label
10 trn1 z10.h, z3.h, z15.b label
16 trn1 z1.h, z2.h label
22 trn1 z1.s, z2.s, z32.s label
28 trn1 p1.s, p2.s, p16.s label
34 trn1 z1.s, z2.s, p3.s label
40 trn1 p1.s, p2.s, z3.s label
50 trn1 z31.d, z31.d, z31.d label
56 trn1 z31.d, z31.d, z31.d label
Dtrn1.s10 trn1 z31.b, z31.b, z31.b label
16 trn1 z31.h, z31.h, z31.h label
22 trn1 z31.s, z31.s, z31.s label
28 trn1 z31.d, z31.d, z31.d label
34 trn1 p15.b, p15.b, p15.b label
40 trn1 p15.s, p15.s, p15.s label
46 trn1 p15.h, p15.h, p15.h label
52 trn1 p15.d, p15.d, p15.d label
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dshuffle-transpose.ll4 ; COST-LABEL: trn1.v8i8
6 ; CODE-LABEL: trn1.v8i8
7 ; CODE: trn1 v0.8b, v0.8b, v1.8b
8 define <8 x i8> @trn1.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
22 ; COST-LABEL: trn1.v16i8
24 ; CODE-LABEL: trn1.v16i8
25 ; CODE: trn1 v0.16b, v0.16b, v1.16b
26 define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
40 ; COST-LABEL: trn1.v4i16
42 ; CODE-LABEL: trn1.v4i16
[all …]
/external/libavc/common/armv8/
Dih264_deblk_luma_av8.s472 trn1 v21.8b, v0.8b, v2.8b
475 trn1 v21.8b, v4.8b, v6.8b
478 trn1 v21.8b, v8.8b, v10.8b
481 trn1 v21.8b, v12.8b, v14.8b
484 trn1 v21.8b, v1.8b, v3.8b
487 trn1 v21.8b, v5.8b, v7.8b
490 trn1 v21.8b, v9.8b, v11.8b
493 trn1 v21.8b, v13.8b, v15.8b
497 trn1 v21.4h, v2.4h, v6.4h
500 trn1 v21.4h, v10.4h, v14.4h
[all …]
Dih264_resi_trans_quant_av8.s104 trn1 v1.4h, v0.4h, v2.4h
106 trn1 v5.4h, v4.4h, v6.4h
109 trn1 v0.2s, v1.2s, v5.2s
111 trn1 v2.2s, v3.2s, v7.2s
128 trn1 v0.4h, v14.4h, v15.4h
130 trn1 v2.4h, v16.4h, v17.4h
133 trn1 v14.2s, v0.2s, v2.2s
135 trn1 v15.2s, v1.2s, v3.2s
306 trn1 v1.4h, v0.4h, v2.4h
308 trn1 v5.4h, v4.4h, v6.4h
[all …]
Dih264_iquant_itrans_recon_av8.s191 trn1 v4.4h, v10.4h, v11.4h
193 trn1 v6.4h, v12.4h, v13.4h
196 trn1 v10.2s, v4.2s, v6.2s // 0
197 trn1 v11.2s, v5.2s, v7.2s // 8
382 trn1 v4.4h, v10.4h, v11.4h
384 trn1 v6.4h, v12.4h, v13.4h
387 trn1 v10.2s, v4.2s, v6.2s // 0
388 trn1 v11.2s, v5.2s, v7.2s // 8
619 trn1 v8.8h, v0.8h, v1.8h
621 trn1 v10.8h, v2.8h, v3.8h
[all …]
Dih264_ihadamard_scaling_av8.s123 trn1 v4.4s, v0.4s, v1.4s
125 trn1 v6.4s, v2.4s, v3.4s
128 trn1 v0.2d, v4.2d, v6.2d
130 trn1 v1.2d, v5.2d, v7.2d
230 trn1 v0.4s, v2.4s, v4.4s
/external/libhevc/common/arm64/
Dihevc_itrans_recon_8x8.s418 trn1 v25.4h, v2.4h, v6.4h
421 trn1 v27.4h, v3.4h, v7.4h
424 trn1 v6.2s, v29.2s, v31.2s
426 trn1 v2.2s, v25.2s, v27.2s
430 trn1 v25.4h, v10.4h, v14.4h
433 trn1 v27.4h, v11.4h, v15.4h
436 trn1 v10.2s, v25.2s, v27.2s
438 trn1 v14.2s, v29.2s, v31.2s
500 trn1 v27.4h, v2.4h, v3.4h
502 trn1 v25.4h, v4.4h, v5.4h
[all …]
Dihevc_itrans_recon_4x4.s164 trn1 v24.4h, v28.4h, v29.4h
166 trn1 v26.4h, v30.4h, v31.4h
168 trn1 v0.2s, v24.2s, v26.2s
170 trn1 v1.2s, v25.2s, v27.2s
200 trn1 v24.4h, v28.4h, v29.4h
202 trn1 v26.4h, v30.4h, v31.4h
204 trn1 v0.2s, v24.2s, v26.2s
206 trn1 v1.2s, v25.2s, v27.2s
Dihevc_itrans_recon_4x4_ttype1.s165 trn1 v24.4h, v28.4h, v29.4h
167 trn1 v26.4h, v30.4h, v31.4h
169 trn1 v21.2s, v24.2s, v26.2s
171 trn1 v22.2s, v25.2s, v27.2s
208 trn1 v24.4h, v28.4h, v29.4h
210 trn1 v26.4h, v30.4h, v31.4h
212 trn1 v0.2s, v24.2s, v26.2s
214 trn1 v1.2s, v25.2s, v27.2s
Dihevc_deblk_chroma_vert.s83 trn1 v29.8b, v5.8b, v17.8b
87 trn1 v29.8b, v16.8b, v4.8b
103 trn1 v29.4h, v5.4h, v16.4h
107 trn1 v29.4h, v17.4h, v4.4h
119 trn1 v29.2s, v5.2s, v17.2s
123 trn1 v29.2s, v16.2s, v4.2s
186 trn1 v29.2s, v0.2s, v1.2s
189 trn1 v29.8b, v0.8b, v1.8b
Dihevc_itrans_recon_16x16.s617 trn1 v26.4h, v4.4h, v12.4h
619 trn1 v28.4h, v5.4h, v13.4h
622 trn1 v4.2s, v26.2s, v28.2s
624 trn1 v12.2s, v27.2s, v29.2s
627 trn1 v26.4h, v18.4h, v20.4h
629 trn1 v28.4h, v19.4h, v21.4h
632 trn1 v18.2s, v26.2s, v28.2s
634 trn1 v20.2s, v27.2s, v29.2s
637 trn1 v26.4h, v22.4h, v30.4h
639 trn1 v28.4h, v23.4h, v31.4h
[all …]
Dihevc_itrans_recon_32x32.s517 trn1 v24.4h, v30.4h, v12.4h
519 trn1 v26.4h, v31.4h, v13.4h
522 trn1 v30.2s, v24.2s, v26.2s
524 trn1 v12.2s, v25.2s, v27.2s
527 trn1 v24.4h, v14.4h, v18.4h
529 trn1 v26.4h, v15.4h, v19.4h
532 trn1 v14.2s, v24.2s, v26.2s
534 trn1 v18.2s, v25.2s, v27.2s
873 trn1 v24.4h, v30.4h, v12.4h
875 trn1 v26.4h, v31.4h, v13.4h
[all …]
Dihevc_deblk_luma_vert.s123 trn1 v24.8b,v15.8b,v1.8b
126 trn1 v2.8b,v29.8b,v0.8b
133 trn1 v24.4h,v29.4h,v2.4h
137 trn1 v1.4h,v15.4h,v0.4h
403 trn1 v20.8b,v29.8b,v21.8b
440 trn1 v0.8b,v29.8b,v5.8b
556 trn1 v6.8b,v29.8b,v3.8b
620 trn1 v0.8b,v29.8b,v5.8b
/external/llvm/test/MC/AArch64/
Dneon-perm.s25 trn1 v0.8b, v1.8b, v2.8b
26 trn1 v0.16b, v1.16b, v2.16b
27 trn1 v0.4h, v1.4h, v2.4h
28 trn1 v0.8h, v1.8h, v2.8h
29 trn1 v0.2s, v1.2s, v2.2s
30 trn1 v0.4s, v1.4s, v2.4s
31 trn1 v0.2d, v1.2d, v2.2d
/external/capstone/suite/MC/AArch64/
Dneon-perm.s.cs9 0x20,0x28,0x02,0x0e = trn1 v0.8b, v1.8b, v2.8b
10 0x20,0x28,0x02,0x4e = trn1 v0.16b, v1.16b, v2.16b
11 0x20,0x28,0x42,0x0e = trn1 v0.4h, v1.4h, v2.4h
12 0x20,0x28,0x42,0x4e = trn1 v0.8h, v1.8h, v2.8h
13 0x20,0x28,0x82,0x0e = trn1 v0.2s, v1.2s, v2.2s
14 0x20,0x28,0x82,0x4e = trn1 v0.4s, v1.4s, v2.4s
15 0x20,0x28,0xc2,0x4e = trn1 v0.2d, v1.2d, v2.2d
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-perm.s25 trn1 v0.8b, v1.8b, v2.8b
26 trn1 v0.16b, v1.16b, v2.16b
27 trn1 v0.4h, v1.4h, v2.4h
28 trn1 v0.8h, v1.8h, v2.8h
29 trn1 v0.2s, v1.2s, v2.2s
30 trn1 v0.4s, v1.4s, v2.4s
31 trn1 v0.2d, v1.2d, v2.2d
/external/libmpeg2/common/armv8/
Dimpeg2_idct.s625 trn1 v25.4h, v2.4h, v6.4h
628 trn1 v27.4h, v3.4h, v7.4h
631 trn1 v6.2s, v29.2s, v31.2s
633 trn1 v2.2s, v25.2s, v27.2s
637 trn1 v25.4h, v10.4h, v14.4h
640 trn1 v27.4h, v11.4h, v15.4h
643 trn1 v10.2s, v25.2s, v27.2s
645 trn1 v14.2s, v29.2s, v31.2s
707 trn1 v27.4h, v2.4h, v3.4h
709 trn1 v25.4h, v4.4h, v5.4h
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-trn.ll5 ;CHECK: trn1.8b
18 ;CHECK: trn1.4h
58 ;CHECK: trn1.16b
71 ;CHECK: trn1.8h
84 ;CHECK: trn1.4s
97 ;CHECK: trn1.4s
112 ;CHECK: trn1.8b
125 ;CHECK: trn1.8h
Dneon-perm.ll696 ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
704 ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
712 ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
720 ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
736 ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
752 ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
760 ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
768 ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
776 ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
792 ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-trn.ll5 ;CHECK: trn1.8b
18 ;CHECK: trn1.4h
58 ;CHECK: trn1.16b
71 ;CHECK: trn1.8h
84 ;CHECK: trn1.4s
97 ;CHECK: trn1.4s
112 ;CHECK: trn1.8b
125 ;CHECK: trn1.8h
Dneon-perm.ll696 ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
704 ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
712 ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
720 ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
736 ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
752 ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
760 ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
768 ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
776 ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
792 ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
[all …]
Dsve-intrinsics-perm-select.ll1210 ; CHECK: trn1 p0.b, p0.b, p1.b
1212 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %a,
1219 ; CHECK: trn1 p0.h, p0.h, p1.h
1221 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.trn1.nxv8i1(<vscale x 8 x i1> %a,
1228 ; CHECK: trn1 p0.s, p0.s, p1.s
1230 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.trn1.nxv4i1(<vscale x 4 x i1> %a,
1237 ; CHECK: trn1 p0.d, p0.d, p1.d
1239 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.trn1.nxv2i1(<vscale x 2 x i1> %a,
1246 ; CHECK: trn1 z0.b, z0.b, z1.b
1248 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %a,
[all …]
/external/llvm/test/CodeGen/X86/
Davx512vl-intrinsics-fast-isel.ll46 %trn1 = trunc i8 %a1 to i4
48 %arg1 = bitcast i4 %trn1 to <4 x i1>
184 %trn1 = trunc i8 %a1 to i2
185 %arg1 = bitcast i2 %trn1 to <2 x i1>
258 %trn1 = trunc i8 %a1 to i4
259 %arg1 = bitcast i4 %trn1 to <4 x i1>
332 %trn1 = trunc i8 %a1 to i2
333 %arg1 = bitcast i2 %trn1 to <2 x i1>
406 %trn1 = trunc i8 %a1 to i4
407 %arg1 = bitcast i4 %trn1 to <4 x i1>
[all …]
/external/eigen/Eigen/src/Core/arch/NEON/
DPacketMath.h674 float64x2_t trn1, trn2;
678 trn1 = vzip1q_f64(vecs[0], vecs[1]);
682 return vaddq_f64(trn1, trn2);
717 float64x2_t trn1 = vzip1q_f64(kernel.packet[0], kernel.packet[1]);
720 kernel.packet[0] = trn1;

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