Searched refs:ttmp0 (Results 1 – 14 of 14) sorted by relevance
| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | trap.s | 15 s_add_u32 ttmp0, ttmp0, 4
127 s_add_u32 ttmp0, ttmp12, 4
131 s_add_u32 ttmp0, ttmp13, 4
135 s_add_u32 ttmp0, ttmp14, 4
139 s_add_u32 ttmp0, ttmp15, 4
|
| D | expressions.s | 319 ttmp0=1
320 v_sin_f32 v0, -[ttmp0]
|
| D | smem.s | 151 s_buffer_store_dword ttmp0, s[92:95], m0
198 s_buffer_load_dword ttmp0, s[92:95], m0
|
| D | smrd.s | 70 s_load_dword ttmp0, s[2:3], s4
|
| D | vop-err.s | 30 v_movreld_b32 v0, ttmp0
|
| /external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| D | trap_gfx9.txt | 7 # GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
64 # GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
67 # GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
70 # GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
73 # GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
|
| D | trap_vi.txt | 7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
| /external/llvm/test/MC/AMDGPU/ |
| D | trap.s | 9 s_add_u32 ttmp0, ttmp0, 4
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | trap_vi.txt | 7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
|
| /external/mesa3d/src/amd/vulkan/ |
| D | radv_debug.c | 917 uint32_t ttmp0 = device->tma_ptr[4]; in radv_check_trap_handler() local
930 uint64_t pc = (ttmp0 | ((ttmp1 & 0x0000ffffull) << 32)) - (pc_rewind * 4); in radv_check_trap_handler()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 68 def TTMP0 : SIReg <"ttmp0", 112>;
|
| /external/mesa3d/src/amd/compiler/ |
| D | aco_ir.h | 389 static constexpr PhysReg ttmp0{112};
|
| D | aco_instruction_selection.cpp | 11983 Operand(0u), Operand(PhysReg{ttmp0}, s2), memory_sync_info(), true); in select_trap_handler_shader()
|
| /external/llvm-project/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 310 ttmp0
|