Searched refs:txr (Results 1 – 10 of 10) sorted by relevance
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_state_init.c | 587 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); in radeonInitState()
588 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); in radeonInitState()
589 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); in radeonInitState()
621 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); in radeonInitState()
622 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); in radeonInitState()
623 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); in radeonInitState()
|
| D | radeon_context.h | 326 struct radeon_state_atom txr[3]; /* for NPOT */ member
|
| D | radeon_blit.c | 417 r100->hw.txr[0].dirty = GL_TRUE; in r100_blit()
|
| D | radeon_texstate.c | 730 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0]; in import_tex_obj_state()
733 RADEON_STATECHANGE( rmesa, txr[unit] ); in import_tex_obj_state()
|
| D | radeon_ioctl.c | 78 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]); in radeonSetUpAtomList()
|
| /external/libchromeos-rs/src/sync/ |
| D | mu.rs | 1467 let (txr, rxr) = channel(); in rw_multi_thread_async()
1469 ex.spawn_ok(reader(Arc::clone(&mu), txr.clone())); in rw_multi_thread_async()
|
| /external/crosvm/cros_async/src/sync/ |
| D | mu.rs | 1346 let (txr, rxr) = channel(); in rw_multi_thread_async()
1348 ex.spawn_ok(reader(Arc::clone(&mu), txr.clone())); in rw_multi_thread_async()
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | iso-639-3_Name_Index.tab | 6957 txr Tartessian Tartessian
|
| D | iso-639-3.tab | 6663 txr I A Tartessian
|
| D | language-subtag-registry | 36028 Subtag: txr
|