Home
last modified time | relevance | path

Searched refs:uadd8 (Results 1 – 25 of 37) sorted by relevance

12

/external/llvm-project/libc/AOR_v20.02/string/arm/
Dstrlen-armv6t2.S60 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
62 uadd8 data1b, data1b, const_m1
68 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
71 uadd8 data1b, data1b, const_m1
77 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
80 uadd8 data1b, data1b, const_m1
87 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
90 uadd8 data1b, data1b, const_m1
Dstrcmp.S194 uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
198 uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
205 uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
208 uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
238 uadd8 syndrome, data1, const_m1 /* Only need GE bits. */
244 uadd8 syndrome, data1, const_m1
344 uadd8 syndrome, data1, const_m1
385 uadd8 syndrome, data1, const_m1
418 uadd8 syndrome, data1, const_m1
459 uadd8 tmp1, data1, const_m1
Dmemchr.S80 uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0
/external/arm-optimized-routines/string/arm/
Dstrlen-armv6t2.S59 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
61 uadd8 data1b, data1b, const_m1
67 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
70 uadd8 data1b, data1b, const_m1
76 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
79 uadd8 data1b, data1b, const_m1
86 uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
89 uadd8 data1b, data1b, const_m1
Dstrcmp.S192 uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
196 uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
203 uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
206 uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
236 uadd8 syndrome, data1, const_m1 /* Only need GE bits. */
242 uadd8 syndrome, data1, const_m1
342 uadd8 syndrome, data1, const_m1
383 uadd8 syndrome, data1, const_m1
416 uadd8 syndrome, data1, const_m1
457 uadd8 tmp1, data1, const_m1
Dmemchr.S78 uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0
/external/llvm-project/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll121 define i32 @uadd8(i32 %a, i32 %b) nounwind {
122 ; CHECK-LABEL: uadd8
123 ; CHECK: uadd8 r0, r0, r1
124 %tmp = call i32 @llvm.arm.uadd8(i32 %a, i32 %b)
438 declare i32 @llvm.arm.uadd8(i32, i32) nounwind
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc100 M(uadd8) \
Dtest-assembler-cond-rd-rn-rm-a32.cc101 M(uadd8) \
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s387 uadd8 r0, r1, r2 label
816 # CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
1256 ….50 - - - - 1.00 - - - - - - uadd8 r0, r1, r2
Dm4-int.s400 uadd8 r0, r1, r2 label
840 # CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
1278 # CHECK-NEXT: 1.00 uadd8 r0, r1, r2
Dcortex-a57-basic-instructions.s774 uadd8 r1, r2, r3
1644 # CHECK-NEXT: 2 2 1.00 * * U uadd8 r1, r2, r3
2521 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd8 r1, r2, r3
Dcortex-a57-thumb.s785 uadd8 r1, r2, r3
1692 # CHECK-NEXT: 2 2 1.00 * * U uadd8 r1, r2, r3
2606 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd8 r1, r2, r3
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs901 0x93,0x1f,0x52,0xe6 = uadd8 r1, r2, r3
/external/vixl/src/aarch32/
Dassembler-aarch32.h3618 void uadd8(Condition cond, Register rd, Register rn, Register rm);
3619 void uadd8(Register rd, Register rn, Register rm) { uadd8(al, rd, rn, rm); } in uadd8() function
Ddisasm-aarch32.h1362 void uadd8(Condition cond, Register rd, Register rn, Register rm);
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s3247 uadd8 r1, r2, r3
3252 @ CHECK: uadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xe6]
Dbasic-thumb2-instructions.s3561 uadd8 r1, r2, r3
3567 @ CHECK: uadd8 r1, r2, r3 @ encoding: [0x82,0xfa,0x43,0xf1]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s3217 uadd8 r1, r2, r3
3222 @ CHECK: uadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xe6]
Dbasic-thumb2-instructions.s3302 uadd8 r1, r2, r3
3308 @ CHECK: uadd8 r1, r2, r3 @ encoding: [0x82,0xfa,0x43,0xf1]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt2210 # CHECK: uadd8 r1, r2, r3
Dthumb2.txt2326 # CHECK: uadd8 r1, r2, r3
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt2326 # CHECK: uadd8 r1, r2, r3
Dbasic-arm-instructions.txt2210 # CHECK: uadd8 r1, r2, r3
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc1135 { /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */
6316 { /* ARM_t2UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */

12