| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-mul.ll | 51 ; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | dp-3source.ll | 61 ; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | aarch64-fix-cortex-a53-835769.ll | 240 ; CHECK-NEXT: umaddl
243 ; CHECK-NOWORKAROUND-NEXT: umaddl
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-mul.ll | 51 ; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | dp-3source.ll | 61 ; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | aarch64-fix-cortex-a53-835769.ll | 240 ; CHECK-NEXT: umaddl
243 ; CHECK-NOWORKAROUND-NEXT: umaddl
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| D | mul_pow2.ll | 183 ; CHECK-NEXT: umaddl x0, w0, w8, x1
189 ; GISEL-NEXT: umaddl x0, w0, w8, x1
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| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 466 umaddl x1, w2, w3, x4
475 ; CHECK: umaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0xa3,0x9b]
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| D | basic-a64-instructions.s | 1610 umaddl x3, w5, w2, x9
1611 umaddl xzr, w10, w11, x12
1612 umaddl x13, wzr, w14, x15
1613 umaddl x16, w17, wzr, x18
1614 umaddl x19, w20, w21, xzr
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 466 umaddl x1, w2, w3, x4
475 ; CHECK: umaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0xa3,0x9b]
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| D | basic-a64-instructions.s | 1627 umaddl x3, w5, w2, x9
1628 umaddl xzr, w10, w11, x12
1629 umaddl x13, wzr, w14, x15
1630 umaddl x16, w17, wzr, x18
1631 umaddl x19, w20, w21, xzr
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| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 524 umaddl x3, w5, w2, x9 label
525 umaddl xzr, w10, w11, x12 label
526 umaddl x13, wzr, w14, x15 label
527 umaddl x16, w17, wzr, x18 label
1841 # CHECK-NEXT: 1 4 1.00 umaddl x3, w5, w2, x9
1842 # CHECK-NEXT: 1 4 1.00 umaddl xzr, w10, w11, x12
1843 # CHECK-NEXT: 1 4 1.00 umaddl x13, wzr, w14, x15
1844 # CHECK-NEXT: 1 4 1.00 umaddl x16, w17, wzr, x18
3024 … - - - - - - - - - 1.00 - umaddl x3, w5, w2, x9
3025 … - - - - - - - - 1.00 - umaddl xzr, w10, w11, x12
[all …]
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| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 628 0xa3,0x24,0xa2,0x9b = umaddl x3, w5, w2, x9
629 0x5f,0x31,0xab,0x9b = umaddl xzr, w10, w11, x12
630 0xed,0x3f,0xae,0x9b = umaddl x13, wzr, w14, x15
631 0x30,0x4a,0xbf,0x9b = umaddl x16, w17, wzr, x18
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 433 # CHECK: umaddl x1, w2, w3, x4
|
| D | basic-a64-instructions.txt | 1188 # CHECK: umaddl x3, w5, w2, x9
1189 # CHECK: umaddl xzr, w10, w11, x12
1190 # CHECK: umaddl x13, wzr, w14, x15
1191 # CHECK: umaddl x16, w17, wzr, x18
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| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 433 # CHECK: umaddl x1, w2, w3, x4
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| D | basic-a64-instructions.txt | 1175 # CHECK: umaddl x3, w5, w2, x9
1176 # CHECK: umaddl xzr, w10, w11, x12
1177 # CHECK: umaddl x13, wzr, w14, x15
1178 # CHECK: umaddl x16, w17, wzr, x18
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 451 COMPARE(umaddl(x0, w1, w2, x3), "umaddl x0, w1, w2, x3"); in TEST()
452 COMPARE(umaddl(x30, w21, w22, x16), "umaddl x30, w21, w22, x16"); in TEST()
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| D | test-cpu-features-aarch64.cc | 522 TEST_NONE(umaddl_0, umaddl(x0, w1, w2, x3))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 991 void umaddl(const Register& xd,
998 umaddl(xd, wn, wm, xzr); in umull()
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| D | assembler-aarch64.cc | 928 void Assembler::umaddl(const Register& xd, in umaddl() function in vixl::aarch64::Assembler
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| D | macro-assembler-aarch64.h | 2623 umaddl(rd, rn, rm, ra); in Umaddl()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3135 void umaddl(const Register& xd,
|
| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 8213 { /* AArch64_UMADDLrrr, ARM64_INS_UMADDL: umaddl $rd, $rn, $rm, $ra */
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 739 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
|