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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dumaxv-diagnostics.s7 umaxv d0, p7, z31.b define
12 umaxv d0, p7, z31.h define
17 umaxv d0, p7, z31.s define
22 umaxv v0.2d, p7, z31.d label
31 umaxv h0, p8, z31.h label
36 umaxv h0, p7.b, z31.h label
41 umaxv h0, p7.q, z31.h label
51 umaxv d0, p7, z31.d define
57 umaxv d0, p7, z31.d define
Dumaxv.s10 umaxv b0, p7, z31.b label
16 umaxv h0, p7, z31.h label
22 umaxv s0, p7, z31.s label
28 umaxv d0, p7, z31.d define
/external/llvm/test/CodeGen/AArch64/
Darm64-umaxv.ll5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
82 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
89 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
197 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
Daarch64-minmaxv.ll78 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
100 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
119 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
135 ; CHECK-NOT: umaxv
324 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]
349 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-umaxv.ll5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll57 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
65 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
81 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
88 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
104 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
111 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
127 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
134 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
194 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
196 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
Dsve-int-reduce-pred.ll145 ; CHECK-NEXT: umaxv b0, p0, z0.b
148 %out = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %pg,
156 ; CHECK-NEXT: umaxv h0, p0, z0.h
159 %out = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %pg,
167 ; CHECK-NEXT: umaxv s0, p0, z0.s
170 %out = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %pg,
178 ; CHECK-NEXT: umaxv d0, p0, z0.d
181 %out = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %pg,
418 declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
419 declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
Dvecreduce-umax-legalization.ll107 ; CHECK-NEXT: umaxv h0, v0.4h
124 ; CHECK-NEXT: umaxv b0, v0.16b
135 ; CHECK-NEXT: umaxv s0, v0.4s
163 ; CHECK-NEXT: umaxv s0, v0.4s
190 ; CHECK-NEXT: umaxv s0, v0.4s
Daarch64-minmaxv.ll47 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
55 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
63 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
139 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]
152 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
Dvecreduce-bool.ll150 ; CHECK-NEXT: umaxv h0, v0.4h
165 ; CHECK-NEXT: umaxv b0, v0.8b
180 ; CHECK-NEXT: umaxv b0, v0.16b
197 ; CHECK-NEXT: umaxv b0, v0.16b
Dsve-fixed-length-int-reduce.ll958 ; CHECK: umaxv b0, v0.8b
967 ; CHECK: umaxv b0, v0.16b
977 ; CHECK-NEXT: umaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
989 ; VBITS_GE_512-NEXT: umaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
999 ; VBITS_EQ_256-DAG: umaxv b[[REDUCE:[0-9]+]], [[PG]], [[MAX]].b
1011 ; VBITS_GE_1024-NEXT: umaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1023 ; VBITS_GE_2048-NEXT: umaxv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1034 ; CHECK: umaxv h0, v0.4h
1043 ; CHECK: umaxv h0, v0.8h
1053 ; CHECK-NEXT: umaxv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
[all …]
Dsve-int-reduce.ll293 ; CHECK-NEXT: umaxv b0, p0, z0.b
304 ; CHECK-NEXT: umaxv h0, p0, z0.h
315 ; CHECK-NEXT: umaxv s0, p0, z0.s
326 ; CHECK-NEXT: umaxv d0, p0, z0.d
Dsve-split-int-reduce.ll189 ; CHECK-NEXT: umaxv h0, p0, z0.h
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs22 0x20,0xa8,0x30,0x2e = umaxv b0, v1.8b
23 0x20,0xa8,0x30,0x6e = umaxv b0, v1.16b
24 0x20,0xa8,0x70,0x2e = umaxv h0, v1.4h
25 0x20,0xa8,0x70,0x6e = umaxv h0, v1.8h
26 0x20,0xa8,0xb0,0x6e = umaxv s0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s57 umaxv b0, v1.8b
58 umaxv b0, v1.16b
59 umaxv h0, v1.4h
60 umaxv h0, v1.8h
61 umaxv s0, v1.4s
Dneon-diagnostics.s3775 umaxv s0, v1.2s
3797 umaxv d0, v1.2d define
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-across.s57 umaxv b0, v1.8b
58 umaxv b0, v1.16b
59 umaxv h0, v1.4h
60 umaxv h0, v1.8h
61 umaxv s0, v1.4s
Dneon-diagnostics.s3715 umaxv s0, v1.2s
3737 umaxv d0, v1.2d define
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dvector-reduce.ll97 ; CODE: umaxv b0, v0.8b
106 ; CODE: umaxv b0, v0.16b
115 ; CODE: umaxv h0, v0.4h
124 ; CODE: umaxv h0, v0.8h
133 ; CODE: umaxv s0, v0.4s
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2250 __ umaxv(b17, v30.V16B()); in GenerateTestSequenceNEON() local
2251 __ umaxv(b23, v12.V8B()); in GenerateTestSequenceNEON() local
2252 __ umaxv(h31, v15.V4H()); in GenerateTestSequenceNEON() local
2253 __ umaxv(h15, v25.V8H()); in GenerateTestSequenceNEON() local
2254 __ umaxv(s18, v21.V4S()); in GenerateTestSequenceNEON() local
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1905 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b
1906 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b
1907 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h
1908 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h
1909 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s
Dlog-disasm1905 0x~~~~~~~~~~~~~~~~ 6e30abd1 umaxv b17, v30.16b
1906 0x~~~~~~~~~~~~~~~~ 2e30a997 umaxv b23, v12.8b
1907 0x~~~~~~~~~~~~~~~~ 2e70a9ff umaxv h31, v15.4h
1908 0x~~~~~~~~~~~~~~~~ 6e70ab2f umaxv h15, v25.8h
1909 0x~~~~~~~~~~~~~~~~ 6eb0aab2 umaxv s18, v21.4s

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