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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duminv-diagnostics.s7 uminv d0, p7, z31.b define
12 uminv d0, p7, z31.h define
17 uminv d0, p7, z31.s define
22 uminv v0.2d, p7, z31.d label
31 uminv h0, p8, z31.h label
36 uminv h0, p7.b, z31.h label
41 uminv h0, p7.q, z31.h label
51 uminv d0, p7, z31.d define
57 uminv d0, p7, z31.d define
Duminv.s10 uminv b0, p7, z31.b label
16 uminv h0, p7, z31.h label
22 uminv s0, p7, z31.s label
28 uminv d0, p7, z31.d define
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-uminv.ll5 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0
10 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: uminv.4h h[[REG:[0-9]+]], v0
33 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: uminv.8h h[[REG:[0-9]+]], v0
54 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: uminv.16b b[[REG:[0-9]+]], v0
75 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
25 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)
33 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
273 ; CHECK: uminv b{{[0-9]+}}, {{v[0-9]+}}.8b
275 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a)
276 %0 = trunc i32 %uminv.i to i8
282 ; CHECK: uminv h{{[0-9]+}}, {{v[0-9]+}}.4h
284 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll8 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
15 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
33 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
41 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
150 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
157 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
173 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
180 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
198 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
200 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
Daarch64-insert-subvector-undef.ll10 %vminv = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %0)
20 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
Dsve-int-reduce-pred.ll233 ; CHECK-NEXT: uminv b0, p0, z0.b
236 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
244 ; CHECK-NEXT: uminv h0, p0, z0.h
247 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
255 ; CHECK-NEXT: uminv s0, p0, z0.s
258 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
266 ; CHECK-NEXT: uminv d0, p0, z0.d
269 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
426 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
427 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
Dvecreduce-bool.ll55 ; CHECK-NEXT: uminv h0, v0.4h
70 ; CHECK-NEXT: uminv b0, v0.8b
85 ; CHECK-NEXT: uminv b0, v0.16b
102 ; CHECK-NEXT: uminv b0, v0.16b
Dsve-fixed-length-int-reduce.ll1268 ; CHECK: uminv b0, v0.8b
1277 ; CHECK: uminv b0, v0.16b
1287 ; CHECK-NEXT: uminv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1299 ; VBITS_GE_512-NEXT: uminv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1309 ; VBITS_EQ_256-DAG: uminv b[[REDUCE:[0-9]+]], [[PG]], [[MIN]].b
1321 ; VBITS_GE_1024-NEXT: uminv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1333 ; VBITS_GE_2048-NEXT: uminv b[[REDUCE:[0-9]+]], [[PG]], [[OP]].b
1344 ; CHECK: uminv h0, v0.4h
1353 ; CHECK: uminv h0, v0.8h
1363 ; CHECK-NEXT: uminv h[[REDUCE:[0-9]+]], [[PG]], [[OP]].h
[all …]
Dsve-int-reduce.ll201 ; CHECK-NEXT: uminv b0, p0, z0.b
212 ; CHECK-NEXT: uminv h0, p0, z0.h
223 ; CHECK-NEXT: uminv s0, p0, z0.s
234 ; CHECK-NEXT: uminv d0, p0, z0.d
Dsve-split-int-reduce.ll136 ; CHECK-NEXT: uminv d0, p0, z0.d
149 ; CHECK-NEXT: uminv d0, p0, z0.d
/external/llvm/test/CodeGen/AArch64/
Darm64-uminv.ll5 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0
10 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: uminv.4h h[[REG:[0-9]+]], v0
33 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: uminv.8h h[[REG:[0-9]+]], v0
54 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: uminv.16b b[[REG:[0-9]+]], v0
75 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
[all …]
Darm64-neon-across.ll21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
25 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)
33 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
273 ; CHECK: uminv b{{[0-9]+}}, {{v[0-9]+}}.8b
275 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a)
276 %0 = trunc i32 %uminv.i to i8
282 ; CHECK: uminv h{{[0-9]+}}, {{v[0-9]+}}.4h
284 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a)
[all …]
Darm64-vecCmpBr.ll9 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
16 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
34 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
42 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
151 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
158 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
174 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
181 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
199 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
201 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
Daarch64-minmaxv.ll220 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
242 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
261 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
277 ; CHECK-NOT: uminv
372 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
397 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs27 0x20,0xa8,0x31,0x2e = uminv b0, v1.8b
28 0x20,0xa8,0x31,0x6e = uminv b0, v1.16b
29 0x20,0xa8,0x71,0x2e = uminv h0, v1.4h
30 0x20,0xa8,0x71,0x6e = uminv h0, v1.8h
31 0x20,0xa8,0xb1,0x6e = uminv s0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s69 uminv b0, v1.8b
70 uminv b0, v1.16b
71 uminv h0, v1.4h
72 uminv h0, v1.8h
73 uminv s0, v1.4s
Dneon-diagnostics.s3776 uminv s0, v1.2s
3798 uminv d0, v1.2d define
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-across.s69 uminv b0, v1.8b
70 uminv b0, v1.16b
71 uminv h0, v1.4h
72 uminv h0, v1.8h
73 uminv s0, v1.4s
Dneon-diagnostics.s3716 uminv s0, v1.2s
3738 uminv d0, v1.2d define
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dvector-reduce.ll52 ; CODE: uminv b0, v0.8b
61 ; CODE: uminv b0, v0.16b
70 ; CODE: uminv h0, v0.4h
79 ; CODE: uminv h0, v0.8h
88 ; CODE: uminv s0, v0.4s
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2267 __ uminv(b0, v17.V16B()); in GenerateTestSequenceNEON() local
2268 __ uminv(b0, v31.V8B()); in GenerateTestSequenceNEON() local
2269 __ uminv(h24, v0.V4H()); in GenerateTestSequenceNEON() local
2270 __ uminv(h29, v14.V8H()); in GenerateTestSequenceNEON() local
2271 __ uminv(s30, v3.V4S()); in GenerateTestSequenceNEON() local
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1922 0x~~~~~~~~~~~~~~~~ 6e31aa20 uminv b0, v17.16b
1923 0x~~~~~~~~~~~~~~~~ 2e31abe0 uminv b0, v31.8b
1924 0x~~~~~~~~~~~~~~~~ 2e71a818 uminv h24, v0.4h
1925 0x~~~~~~~~~~~~~~~~ 6e71a9dd uminv h29, v14.8h
1926 0x~~~~~~~~~~~~~~~~ 6eb1a87e uminv s30, v3.4s
Dlog-disasm1922 0x~~~~~~~~~~~~~~~~ 6e31aa20 uminv b0, v17.16b
1923 0x~~~~~~~~~~~~~~~~ 2e31abe0 uminv b0, v31.8b
1924 0x~~~~~~~~~~~~~~~~ 2e71a818 uminv h24, v0.4h
1925 0x~~~~~~~~~~~~~~~~ 6e71a9dd uminv h29, v14.8h
1926 0x~~~~~~~~~~~~~~~~ 6eb1a87e uminv s30, v3.4s

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