| /external/python/cpython3/Lib/lib2to3/tests/ |
| D | test_fixers.py | 41 def warns(self, before, after, message, unchanged=False): argument
44 if not unchanged:
48 self.warns(before, before, message, unchanged=True)
50 def unchanged(self, before, ignore_warnings=False): member in FixerTestCase
240 self.unchanged(s)
244 self.unchanged(s)
248 self.unchanged(s)
252 self.unchanged(s)
256 self.unchanged(s)
260 self.unchanged(s)
[all …]
|
| /external/python/cpython2/Lib/lib2to3/tests/ |
| D | test_fixers.py | 42 def warns(self, before, after, message, unchanged=False): argument
45 if not unchanged:
49 self.warns(before, before, message, unchanged=True)
51 def unchanged(self, before, ignore_warnings=False): member in FixerTestCase
241 self.unchanged(s)
245 self.unchanged(s)
249 self.unchanged(s)
253 self.unchanged(s)
257 self.unchanged(s)
261 self.unchanged(s)
[all …]
|
| /external/skia/resources/sksl/folding/ |
| D | ShortCircuitBoolFolding.sksl | 12 if (true ^^ expr) { ++bad; } else { ++ok; } // -> unchanged
17 if (false == expr) { ++bad; } else { ++ok; } // -> unchanged
18 if (true != expr) { ++bad; } else { ++ok; } // -> unchanged
24 if (expr ^^ true ) { ++bad; } else { ++ok; } // -> unchanged
29 if (expr == false) { ++bad; } else { ++ok; } // -> unchanged
30 if (expr != true ) { ++bad; } else { ++ok; } // -> unchanged
39 bool(a = b) || true; // -> unchanged
|
| /external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-legalize-exts.mir | 35 ; G_ZEXT with s16 is legal, so we should find it unchanged in the output
59 ; G_SEXT with s8 is legal, so we should find it unchanged in the output
109 ; G_ANYEXT with s1 is legal, so we should find it unchanged in the output
133 ; G_ZEXT from s8 to s16 is legal, so we should find it unchanged in the output
157 ; G_SEXT from s1 to s16 is legal, so we should find it unchanged in the output
181 ; G_ANYEXT from s1 to s8 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-binops-neon.mir | 27 ; G_ADD with s64 is legal, so we should find it unchanged in the output
51 ; G_SUB with s64 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-control-flow.mir | 31 ; G_BRCOND with s1 is legal, so we should find it unchanged in the output
76 ; G_PHI with s32 is legal, so we should find it unchanged in the output
113 ; G_PHI with p0 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-casts.mir | 27 ; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
49 ; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-binops.mir | 123 ; G_ADD with s32 is legal, so we should find it unchanged in the output
212 ; G_SUB with s32 is legal, so we should find it unchanged in the output
301 ; G_MUL with s32 is legal, so we should find it unchanged in the output
390 ; G_AND with s32 is legal, so we should find it unchanged in the output
514 ; G_OR with s32 is legal, so we should find it unchanged in the output
638 ; G_XOR with s32 is legal, so we should find it unchanged in the output
698 ; G_LSHR with s32 is legal, so we should find it unchanged in the output
723 ; G_ASHR with s32 is legal, so we should find it unchanged in the output
748 ; G_SHL with s32 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-cmp.mir | 92 ; G_ICMP with s32 is legal, so we should find it unchanged in the output
118 ; G_ICMP with p0 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-select.mir | 31 ; G_SELECT with s32 is legal, so we should find it unchanged in the output
57 ; G_SELECT with p0 is legal, so we should find it unchanged in the output
|
| D | arm-legalize-globals.mir | 24 ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
|
| /external/mesa3d/src/intel/compiler/ |
| D | test_eu_compact.cpp | 46 brw_compact_inst unchanged; in test_compact_instruction() local
47 memset(&unchanged, 0xd0, sizeof(unchanged)); in test_compact_instruction()
49 if (memcmp(&unchanged, &dst, sizeof(dst))) { in test_compact_instruction()
|
| /external/icu/icu4j/tools/misc/src/com/ibm/icu/dev/tool/translit/ |
| D | UnicodeSetClosure.java | 253 UnicodeSet unchanged = new UnicodeSet(); // UNCHANGED[lc][mode]; in close2() local
254 int count = unchanged.getRangeCount(); in close2()
256 int start = unchanged.getRangeStart(i); in close2()
257 int end = unchanged.getRangeEnd(i); in close2()
|
| /external/autotest/site_utils/stable_images/ |
| D | assign_stable_images.py | 323 unchanged = 0
335 unchanged += 1
337 logging.info('%d boards are unchanged', unchanged)
|
| /external/icu/tools/icu4c_srcgen/doc_patches/patches/unicode/ |
| D | uloc.h.patch | 4 * and unchanged even when uloc_setDefault() is called.
|
| /external/pdfium/testing/resources/javascript/ |
| D | icons_expected.txt | 11 Alert: name is unchanged from undefined
|
| /external/XNNPACK/src/f32-raddexpminusmax/ |
| D | avx2-p5.c.in | 100 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
155 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
201 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
204 // Accumulate computed exponents. And addend with mask to leave unmasked 32-bit lanes unchanged.
|
| /external/XNNPACK/src/f32-raddstoreexpminusmax/ |
| D | avx2-p5.c.in | 101 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
162 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
212 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
218 // Accumulate computed exponents. And addend with mask to leave unmasked 32-bit lanes unchanged.
|
| /external/autotest/server/site_tests/autoupdate_DataPreserved/ |
| D | control.full | 15 unchanged after an update.
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | expand-condsets-def-undef.mir | 34 ; Check that this instruction is unchanged (remains unpredicated)
|
| D | anti-dep-partial.mir | 29 ; unchanged. Check that the renaming of d11 does not happen.
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | peephole-callee-save-regalloc.mir | 7 # Check that register class for %5 is unchanged as 'tcgpr'
|
| /external/llvm/test/CodeGen/MIR/Hexagon/ |
| D | anti-dep-partial.mir | 30 ; unchanged. Check that the renaming of d11 does not happen.
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | extractvalue.ll | 90 ; The load should be left unchanged since both parts are needed.
103 ; The load volatile should be left unchanged.
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | extractvalue.ll | 90 ; The load should be left unchanged since both parts are needed.
103 ; The load volatile should be left unchanged.
|