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Searched refs:update_pred (Results 1 – 25 of 28) sorted by relevance

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/external/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c75 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); in r700_bytecode_alu_build()
122 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1); in r700_bytecode_alu_read()
Dr600_asm.h62 unsigned update_pred; member
Deg_asm.c329 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); in eg_bytecode_alu_build()
Dr600_asm.c1659 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); in r600_bytecode_alu_build()
2276 alu->update_pred ? 'P':' ', in r600_bytecode_disasm()
2838 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1); in r600_bytecode_alu_read()
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_builder.cpp436 .UPDATE_PRED(bc.update_pred) in build_alu()
451 .UPDATE_PRED(bc.update_pred) in build_alu()
465 .UPDATE_PRED(bc.update_pred) in build_alu()
480 .UPDATE_PRED(bc.update_pred) in build_alu()
Dsb_bc.h529 unsigned update_pred:1; member
558 update_pred = 0; in clear()
Dsb_bc_decoder.cpp377 bc.update_pred = w1.get_UPDATE_PRED(); in decode_alu()
396 bc.update_pred = w1.get_UPDATE_PRED(); in decode_alu()
Dsb_bc_dump.cpp381 s << (n.bc.update_pred ? "P" : " "); in dump()
Dsb_bc_finalize.cpp340 n->bc.update_pred = (n->dst[1] != NULL); in finalize_alu_group()
Dsb_bc_parser.cpp427 if (n->bc.update_pred) in prepare_alu_group()
Dsb_expr.cpp1330 a->bc.update_pred = 0; in convert_predset_to_set()
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td126 bits<1> update_pred;
133 let Word1{3} = update_pred;
DR600ExpandSpecialInstrs.cpp114 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1); in runOnMachineFunction()
DR600Instructions.td114 let update_pred = 0;
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
DR600InstrInfo.cpp1316 OPERAND_CASE(AMDGPU::OpName::update_pred) in getSlotedOps()
1357 AMDGPU::OpName::update_pred, in buildSlotOfVectorInstruction()
DEvergreenInstructions.td418 let update_pred = 0;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td135 bits<1> update_pred;
142 let Word1{3} = update_pred;
DR600ExpandSpecialInstrs.cpp129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
DR600InstrInfo.cpp1294 OPERAND_CASE(R600::OpName::update_pred) in getSlotedOps()
1335 R600::OpName::update_pred, in buildSlotOfVectorInstruction()
DR600Instructions.td124 let update_pred = 0;
147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td135 bits<1> update_pred;
142 let Word1{3} = update_pred;
DR600ExpandSpecialInstrs.cpp129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
DR600InstrInfo.cpp1293 OPERAND_CASE(R600::OpName::update_pred) in getSlotedOps()
1334 R600::OpName::update_pred, in buildSlotOfVectorInstruction()
DR600Instructions.td124 let update_pred = 0;
147 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
154 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
DEvergreenInstructions.td492 let update_pred = 0;

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