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Searched refs:uqincd (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duqincd.s14 uqincd x0 label
20 uqincd x0, all label
26 uqincd x0, all, mul #1 label
32 uqincd x0, all, mul #16 label
43 uqincd w0 label
49 uqincd w0, all label
55 uqincd w0, all, mul #1 label
61 uqincd w0, all, mul #16 label
67 uqincd w0, pow2 label
73 uqincd w0, pow2, mul #16 label
[all …]
Duqincd-diagnostics.s6 uqincd wsp label
11 uqincd sp label
16 uqincd z0.s label
25 uqincd x0, w0 label
30 uqincd w0, w0 label
35 uqincd x0, x0 label
44 uqincd x0, all, mul #-1 label
49 uqincd x0, all, mul #0 label
54 uqincd x0, all, mul #17 label
63 uqincd x0, vl512 label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-uqinc.ll44 define <vscale x 2 x i64> @uqincd(<vscale x 2 x i64> %a) {
45 ; CHECK-LABEL: uqincd:
46 ; CHECK: uqincd z0.d, vl2, mul #3
48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %a,
150 ; CHECK: uqincd w0, vl16, mul #10
152 %out = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %a, i32 9, i32 10)
158 ; CHECK: uqincd x0, vl32, mul #11
160 %out = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %a, i32 10, i32 11)
235 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32, i32)
244 declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32, i32)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td886 defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd", int_aarch64_sve_uqincd_n32>;
890 defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd", int_aarch64_sve_uqincd_n64>;
907 defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64, int_aarch64_sve_uqincd, nxv2i64>;
/external/vixl/test/aarch64/
Dtest-api-movprfx-aarch64.cc1193 __ uqincd(z27.VnD(), SVE_MUL3); in TEST() local
1594 __ uqincd(z13.VnD(), SVE_MUL3); in TEST() local
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1332 defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd", int_aarch64_sve_uqincd_n32>;
1336 defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd", int_aarch64_sve_uqincd_n64>;
1353 defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64, int_aarch64_sve_uqincd, nxv2i64>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h5716 void uqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
5720 void uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
Dassembler-sve-aarch64.cc486 V(uqincd, (rdn.IsX() ? UQINCD_r_rs_x : UQINCD_r_rs_uw))
539 V(uqincd, UQINC, D)
Dmacro-assembler-aarch64.h6189 uqincd(rdn, pattern, multiplier);
6194 uqincd(zdn, pattern, multiplier);
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12608 "decw\006uqincb\006uqincd\006uqinch\006uqincp\006uqincw\006uqrshl\007uqr"
19622 …{ 6565 /* uqincd */, AArch64::UQINCD_WPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19623 …{ 6565 /* uqincd */, AArch64::UQINCD_XPiI, Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1, AMFBS_H…
19624 …{ 6565 /* uqincd */, AArch64::UQINCD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__imm_95_31__imm_95_…
19625 …{ 6565 /* uqincd */, AArch64::UQINCD_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19626 …{ 6565 /* uqincd */, AArch64::UQINCD_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1, AMF…
19627 …{ 6565 /* uqincd */, AArch64::UQINCD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__imm…
19628 …{ 6565 /* uqincd */, AArch64::UQINCD_WPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19629 …{ 6565 /* uqincd */, AArch64::UQINCD_XPiI, Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3, A…
19630 …{ 6565 /* uqincd */, AArch64::UQINCD_ZPiI, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__Imm…
[all …]
DAArch64GenAsmWriter.inc22827 /* 13626 */ "uqincd $\x01\0"
22828 /* 13636 */ "uqincd $\x01, $\xFF\x03\x0E\0"
22829 /* 13652 */ "uqincd $\xFF\x01\x10\0"
22830 /* 13664 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
DAArch64GenAsmWriter1.inc23548 /* 13604 */ "uqincd $\x01\0"
23549 /* 13614 */ "uqincd $\x01, $\xFF\x03\x0E\0"
23550 /* 13630 */ "uqincd $\xFF\x01\x10\0"
23551 /* 13642 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc817 "llvm.aarch64.sve.uqincd",
818 "llvm.aarch64.sve.uqincd.n32",
819 "llvm.aarch64.sve.uqincd.n64",
10950 47, // llvm.aarch64.sve.uqincd
10951 47, // llvm.aarch64.sve.uqincd.n32
10952 47, // llvm.aarch64.sve.uqincd.n64