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Searched refs:uqshll (Results 1 – 8 of 8) sorted by relevance

/external/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/
Dscalar-shifts.c224 return uqshll(value, 16); in test_uqshll()
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dscalar-shifts.ll231 ; CHECK-NEXT: uqshll r0, r1, #16
237 %3 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %2, i32 %1, i32 16)
247 declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32)
/external/llvm-project/llvm/test/MC/ARM/
Dmve-scalar-shift.s154 # CHECK: uqshll lr, r7, #7 @ encoding: [0x5f,0xea,0xcf,0x17]
156 uqshll lr, r7, #7 label
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-scalar-shift.txt82 # CHECK: uqshll lr, r7, #7 @ encoding: [0x5f,0xea,0xcf,0x17]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td555 def MVE_UQSHLL : MVE_ScalarShiftDRegImm<"uqshll", 0b00, 0b1>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td595 def MVE_UQSHLL : MVE_ScalarShiftDRegImm<"uqshll", 0b00, 0b1>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9916 "hll\005uqsax\005uqshl\006uqshll\007uqsub16\006uqsub8\005urshr\006urshrl"
11523 …{ 1845 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3…
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc1614 "llvm.arm.mve.uqshll",
11747 1, // llvm.arm.mve.uqshll