Searched refs:urshrl (Results 1 – 8 of 8) sorted by relevance
| /external/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ |
| D | scalar-shifts.c | 253 return urshrl(value, 6); in test_urshrl()
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| /external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
| D | scalar-shifts.ll | 264 ; CHECK-NEXT: urshrl r0, r1, #6
270 %3 = call { i32, i32 } @llvm.arm.mve.urshrl(i32 %2, i32 %1, i32 6)
280 declare { i32, i32 } @llvm.arm.mve.urshrl(i32, i32, i32)
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | mve-scalar-shift.s | 162 # CHECK: urshrl r0, r9, #29 @ encoding: [0x51,0xea,0x5f,0x79]
164 urshrl r0, r9, #29 label
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | mve-scalar-shift.txt | 90 # CHECK: urshrl r0, r9, #29 @ encoding: [0x51,0xea,0x5f,0x79]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrMVE.td | 556 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrMVE.td | 596 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9916 "hll\005uqsax\005uqshl\006uqshll\007uqsub16\006uqsub8\005urshr\006urshrl"
11529 …{ 1873 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3…
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| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1616 "llvm.arm.mve.urshrl",
11749 1, // llvm.arm.mve.urshrl
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