| /external/llvm/test/MC/ARM/ |
| D | v7k-dsp.s | 3 @ CHECK: usad8 r2, r1, r4
4 usad8 r2, r1, r4
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| D | basic-arm-instructions.s | 3374 usad8 r2, r1, r4
3379 @ CHECK: usad8 r2, r1, r4 @ encoding: [0x11,0xf4,0x82,0xe7]
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| D | basic-thumb2-instructions.s | 3501 usad8 r1, r9, r7
3507 @ CHECK: usad8 r1, r9, r7 @ encoding: [0x79,0xfb,0x07,0xf1]
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | v7k-dsp.s | 3 @ CHECK: usad8 r2, r1, r4
4 usad8 r2, r1, r4
|
| D | basic-arm-instructions.s | 3404 usad8 r2, r1, r4
3409 @ CHECK: usad8 r2, r1, r4 @ encoding: [0x11,0xf4,0x82,0xe7]
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| D | basic-thumb2-instructions.s | 3760 usad8 r1, r9, r7
3766 @ CHECK: usad8 r1, r9, r7 @ encoding: [0x79,0xfb,0x07,0xf1]
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 165 ; CHECK: usad8 r0, r0, r1
167 %tmp = call i32 @llvm.arm.usad8(i32 %a, i32 %b)
444 declare i32 @llvm.arm.usad8(i32, i32) nounwind readnone
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 91 M(usad8) \
|
| D | test-assembler-cond-rd-rn-rm-a32.cc | 92 M(usad8) \
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 407 usad8 r0, r1, r2 label
835 # CHECK-NEXT: 1 2 1.00 usad8 r0, r1, r2
1275 ….50 - - - - 1.00 - - - - - - usad8 r0, r1, r2
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| D | m4-int.s | 420 usad8 r0, r1, r2 label
859 # CHECK-NEXT: 1 1 1.00 usad8 r0, r1, r2
1297 # CHECK-NEXT: 1.00 usad8 r0, r1, r2
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| D | cortex-a57-basic-instructions.s | 812 usad8 r2, r1, r4
1682 # CHECK-NEXT: 1 3 1.00 usad8 r2, r1, r4
2559 # CHECK-NEXT: - - - - 1.00 - - - usad8 r2, r1, r4
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| D | cortex-a57-thumb.s | 837 usad8 r1, r9, r7
1744 # CHECK-NEXT: 1 3 1.00 usad8 r1, r9, r7
2658 # CHECK-NEXT: - - - - 1.00 - - - usad8 r1, r9, r7
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 1134 0x79,0xfb,0x07,0xf1 = usad8 r1, r9, r7
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| D | basic-arm-instructions.s.cs | 939 0x11,0xf4,0x82,0xe7 = usad8 r2, r1, r4
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3712 void usad8(Condition cond, Register rd, Register rn, Register rm);
3713 void usad8(Register rd, Register rn, Register rm) { usad8(al, rd, rn, rm); } in usad8() function
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| D | disasm-aarch32.h | 1412 void usad8(Condition cond, Register rd, Register rn, Register rm);
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2367 # CHECK: usad8 r2, r1, r4
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| D | thumb2.txt | 2502 # CHECK: usad8 r1, r9, r7
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2502 # CHECK: usad8 r1, r9, r7
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| D | basic-arm-instructions.txt | 2367 # CHECK: usad8 r2, r1, r4
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 1195 { /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */
6376 { /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 1195 { /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */
6376 { /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2214 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2517 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",
|