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Searched refs:uzp1 (Results 1 – 25 of 64) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duzp1-diagnostics.s4 uzp1 z10.h, z22.h, z31.x label
10 uzp1 z10.h, z3.h, z15.b label
16 uzp1 z1.h, z2.h label
22 uzp1 z1.s, z2.s, z32.s label
28 uzp1 p1.s, p2.s, p16.s label
34 uzp1 z1.s, z2.s, p3.s label
40 uzp1 p1.s, p2.s, z3.s label
50 uzp1 z31.d, z31.d, z31.d label
56 uzp1 z31.d, z31.d, z31.d label
Duzp1.s10 uzp1 z31.b, z31.b, z31.b label
16 uzp1 z31.h, z31.h, z31.h label
22 uzp1 z31.s, z31.s, z31.s label
28 uzp1 z31.d, z31.d, z31.d label
34 uzp1 p15.b, p15.b, p15.b label
40 uzp1 p15.s, p15.s, p15.s label
46 uzp1 p15.h, p15.h, p15.h label
52 uzp1 p15.d, p15.d, p15.d label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-split-trunc.ll7 ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
16 ; CHECK-NEXT: uzp1 z2.h, z2.h, z3.h
17 ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
18 ; CHECK-NEXT: uzp1 z0.b, z0.b, z2.b
27 ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
36 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
45 ; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
46 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
47 ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
56 ; CHECK-NEXT: uzp1 z6.s, z6.s, z7.s
[all …]
Dsve-fixed-length-trunc.ll31 ; CHECK-NEXT: uzp1 z0.b, [[A_HALFS]].b, [[A_HALFS]].b
43 ; VBITS_GE_512: uzp1 [[A_BYTES:z[0-9]+]].b, [[A_HALFS]].b, [[A_HALFS]].b
57 ; VBITS_GE_1024: uzp1 [[A_BYTES:z[0-9]+]].b, [[A_HALFS]].b, [[A_HALFS]].b
71 ; VBITS_GE_2048: uzp1 [[A_BYTES:z[0-9]+]].b, [[A_HALFS]].b, [[A_HALFS]].b
88 ; CHECK-NEXT: uzp1 [[A_HALFS:z[0-9]+]].h, [[A_WORDS]].h, [[A_WORDS]].h
89 ; CHECK-NEXT: uzp1 z0.b, [[A_HALFS]].b, [[A_HALFS]].b
100 ; VBITS_GE_512-NEXT: uzp1 [[A_HALFS:z[0-9]+]].h, [[A_WORDS]].h, [[A_WORDS]].h
101 ; VBITS_GE_512-NEXT: uzp1 z0.b, [[A_HALFS]].b, [[A_HALFS]].b
113 ; VBITS_GE_1024: uzp1 [[A_HALFS:z[0-9]+]].h, [[A_WORDS]].h, [[A_WORDS]].h
114 ; VBITS_GE_1024: uzp1 [[A_BYTES:z[0-9]+]].b, [[A_HALFS]].b, [[A_HALFS]].b
[all …]
Dsve-split-fcvt.ll93 ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
107 ; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
108 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
109 ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
121 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
133 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
147 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
148 ; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s
163 ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
177 ; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
[all …]
Darm64-uzp.ll5 ;CHECK: uzp1.8b
18 ;CHECK: uzp1.4h
31 ;CHECK: uzp1.16b
44 ;CHECK: uzp1.8h
57 ;CHECK: uzp1.4s
70 ;CHECK: uzp1.4s
85 ;CHECK: uzp1.8b
98 ;CHECK: uzp1.8h
Dsve-trunc.ll85 ; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s
102 ; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s
105 ; CHECK-NEXT: uzp1 p0.s, p0.s, p2.s
106 ; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h
134 ; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s
136 ; CHECK-NEXT: uzp1 p3.s, p4.s, p3.s
138 ; CHECK-NEXT: uzp1 p2.s, p4.s, p2.s
141 ; CHECK-NEXT: uzp1 p0.s, p0.s, p4.s
143 ; CHECK-NEXT: uzp1 p1.h, p3.h, p1.h
144 ; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h
[all …]
Darm64-convert-v4f64.ll10 ; CHECK: uzp1 v0.4h, v[[XTN1]].4h, v[[XTN0]].4h
26 ; CHECK-DAG: uzp1 v[[UZP0:[0-9]+]].4h, v[[XTN1]].4h, v[[XTN0]].4h
27 ; CHECK-DAG: uzp1 v[[UZP1:[0-9]+]].4h, v[[XTN3]].4h, v[[XTN2]].4h
28 ; CHECK: uzp1 v0.8b, v[[UZP1:[0-9]+]].8b, v[[UZP0:[0-9]+]].8b
62 ; CHECK: uzp1 v0.4h, v[[XTN1]].4h, v[[XTN0]].4h
Dsve-fixed-length-int-div.ll47 ; CHECK-NEXT: uzp1 [[RES_HI:z[0-9]+]].h, [[RES_HI_LO]].h, [[RES_HI_HI]].h
48 ; CHECK-NEXT: uzp1 [[RES_LO:z[0-9]+]].h, [[RES_LO_LO]].h, [[RES_LO_HI]].h
49 ; CHECK-NEXT: uzp1 z0.b, [[RES_LO]].b, [[RES_HI]].b
74 ; CHECK-NEXT: uzp1 [[RES_HI:z[0-9]+]].h, [[RES_HI_LO]].h, [[RES_HI_HI]].h
75 ; CHECK-NEXT: uzp1 [[RES_LO:z[0-9]+]].h, [[RES_LO_LO]].h, [[RES_LO_HI]].h
76 ; CHECK-NEXT: uzp1 z0.b, [[RES_LO]].b, [[RES_HI]].b
104 ; CHECK-NEXT: uzp1 [[RES_HI:z[0-9]+]].h, [[RES_HI_LO]].h, [[RES_HI_HI]].h
105 ; CHECK-NEXT: uzp1 [[RES_LO:z[0-9]+]].h, [[RES_LO_LO]].h, [[RES_LO_HI]].h
106 ; CHECK-NEXT: uzp1 [[RES:z[0-9]+]].b, [[RES_LO]].b, [[RES_HI]].b
138 ; VBITS_GE_512-NEXT: uzp1 [[RES_HI:z[0-9]+]].h, [[RES_HI_LO]].h, [[RES_HI_HI]].h
[all …]
Dconcat_vector-truncate-combine.ll10 ; CHECK-NEXT: uzp1.4s v0, v0, v1
22 ; CHECK-NEXT: uzp1.8h v0, v0, v1
Dneon-perm.ll24 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
32 ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
40 ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
48 ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
64 ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
80 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
88 ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
96 ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
104 ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
120 ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
[all …]
Dvcvt-oversize.ll12 ; CHECK-DAG: uzp1 v0.8b, v[[TMP]].8b, v[[TMP2]].8b
Dbitcast-promote-widen.ll23 ; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
Daarch64-vuzp.ll6 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
28 ; CHECK-NOT: uzp1
Dsve-intrinsics-perm-select.ll1452 ; CHECK: uzp1 p0.b, p0.b, p1.b
1454 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %a,
1461 ; CHECK: uzp1 p0.h, p0.h, p1.h
1463 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.uzp1.nxv8i1(<vscale x 8 x i1> %a,
1470 ; CHECK: uzp1 p0.s, p0.s, p1.s
1472 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.uzp1.nxv4i1(<vscale x 4 x i1> %a,
1479 ; CHECK: uzp1 p0.d, p0.d, p1.d
1481 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.uzp1.nxv2i1(<vscale x 2 x i1> %a,
1488 ; CHECK: uzp1 z0.b, z0.b, z1.b
1490 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %a,
[all …]
Dllvm-ir-to-intrinsic.ll28 ; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
29 ; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
30 ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
46 ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
130 ; CHECK-NEXT: uzp1 z2.h, z2.h, z6.h
131 ; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h
132 ; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b
151 ; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
207 ; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
208 ; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
[all …]
/external/llvm/test/MC/AArch64/
Dneon-perm.s9 uzp1 v0.8b, v1.8b, v2.8b
10 uzp1 v0.16b, v1.16b, v2.16b
11 uzp1 v0.4h, v1.4h, v2.4h
12 uzp1 v0.8h, v1.8h, v2.8h
13 uzp1 v0.2s, v1.2s, v2.2s
14 uzp1 v0.4s, v1.4s, v2.4s
15 uzp1 v0.2d, v1.2d, v2.2d
/external/capstone/suite/MC/AArch64/
Dneon-perm.s.cs2 0x20,0x18,0x02,0x0e = uzp1 v0.8b, v1.8b, v2.8b
3 0x20,0x18,0x02,0x4e = uzp1 v0.16b, v1.16b, v2.16b
4 0x20,0x18,0x42,0x0e = uzp1 v0.4h, v1.4h, v2.4h
5 0x20,0x18,0x42,0x4e = uzp1 v0.8h, v1.8h, v2.8h
6 0x20,0x18,0x82,0x0e = uzp1 v0.2s, v1.2s, v2.2s
7 0x20,0x18,0x82,0x4e = uzp1 v0.4s, v1.4s, v2.4s
8 0x20,0x18,0xc2,0x4e = uzp1 v0.2d, v1.2d, v2.2d
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-perm.s9 uzp1 v0.8b, v1.8b, v2.8b
10 uzp1 v0.16b, v1.16b, v2.16b
11 uzp1 v0.4h, v1.4h, v2.4h
12 uzp1 v0.8h, v1.8h, v2.8h
13 uzp1 v0.2s, v1.2s, v2.2s
14 uzp1 v0.4s, v1.4s, v2.4s
15 uzp1 v0.2d, v1.2d, v2.2d
/external/llvm/test/CodeGen/AArch64/
Darm64-uzp.ll5 ;CHECK: uzp1.8b
18 ;CHECK: uzp1.4h
31 ;CHECK: uzp1.16b
44 ;CHECK: uzp1.8h
57 ;CHECK: uzp1.4s
70 ;CHECK: uzp1.4s
85 ;CHECK: uzp1.8b
98 ;CHECK: uzp1.8h
Dconcat_vector-truncate-combine.ll10 ; CHECK-NEXT: uzp1.4s v0, v0, v1
22 ; CHECK-NEXT: uzp1.8h v0, v0, v1
Dneon-perm.ll24 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
32 ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
40 ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
48 ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
64 ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
80 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
88 ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
96 ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
104 ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
120 ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
[all …]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s291 uzp1 v30.8b, v30.8b, v30.8b
292 uzp1 v31.8b, v31.8b, v31.8b
293 uzp1 v28.8b, v28.8b, v28.8b
294 uzp1 v29.8b, v29.8b, v29.8b
295 uzp1 v26.8b, v26.8b, v26.8b
296 uzp1 v27.8b, v27.8b, v27.8b
297 uzp1 v24.8b, v24.8b, v24.8b
298 uzp1 v25.8b, v25.8b, v25.8b
Dih264_iquant_itrans_recon_dc_av8.s253 uzp1 v1.16b, v1.16b, v3.16b
254 uzp1 v2.16b, v2.16b, v3.16b
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dpostlegalizer-lowering-uzp.mir109 ; Make sure that we can still produce a uzp1/uzp2 with undef indices.
133 ; Make sure that we can still produce a uzp1/uzp2 with undef indices.

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