| /external/zstd/build/VS_scripts/ |
| D | build.VS2012.cmd | 4 call "%~p0%build.generic.cmd" VS2012 Win32 Release v110
6 call "%~p0%build.generic.cmd" VS2012 x64 Release v110
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| D | build.generic.cmd | 25 echo msbuild_toolset: Platform Toolset (v100, v110, v120, v140, v141)
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | reserve-vgpr-for-sgpr-spill.ll | 35 ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
80 ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
122 ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
171 ,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
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| /external/python/cpython2/PCbuild/ |
| D | env.bat | 8 rem 'v110', 'v120' or 'v140') to the build script. Note that no toolset
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| /external/python/cpython3/PCbuild/ |
| D | env.bat | 8 rem 'v110', 'v120' or 'v140') to the build script.
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | late_instr.ll | 140 %v110 = add nuw nsw i32 %v78, 1
141 %v111 = getelementptr <16 x i32>, <16 x i32>* %v62, i32 %v110
142 %v112 = getelementptr <16 x i32>, <16 x i32>* %v60, i32 %v110
143 %v113 = getelementptr <16 x i32>, <16 x i32>* %v61, i32 %v110
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| D | lsr-post-inc-cross-use-offsets.ll | 173 %v110 = add i32 %v94, %v33
174 %v111 = add nsw i32 %v110, -129
178 %v115 = add nsw i32 %v110, -128
183 %v120 = add nsw i32 %v110, -127
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| D | aggr-licm.ll | 130 %v110 = or i64 %v109, %v99
131 %v111 = or i64 %v110, %v105
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| D | registerscavenger-fail1.ll | 212 %v110 = mul i32 %v108, 232
233 %v122 = mul i32 %v110, %v121
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| D | swp-epilog-phi7.ll | 137 %v110 = phi <16 x i32>* [ %v81, %b1 ], [ %v123, %b2 ]
150 %v123 = getelementptr inbounds <16 x i32>, <16 x i32>* %v110, i32 1
151 %v124 = load <16 x i32>, <16 x i32>* %v110, align 64, !tbaa !0
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| D | SUnit-boundary-prob.ll | 146 %v110 = bitcast i32* %v109 to <16 x i32>*
147 store <16 x i32> %v107, <16 x i32>* %v110, align 64, !tbaa !6
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| D | cext-ice.ll | 226 %v110 = load i32, i32* %v13, align 8, !tbaa !0
227 store volatile i32 %v110, i32* %v4, align 4, !tbaa !0
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| D | swp-sigma.ll | 164 %v110 = getelementptr inbounds <16 x i32>, <16 x i32>* %v42, i32 1
167 %v113 = select i1 %v109, <16 x i32>* %v110, <16 x i32>* %v42
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| D | large-number-of-preds.ll | 178 %v110 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 60
179 store float %v109, float* %v110, align 16, !tbaa !0
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| D | bug14859-split-const-block-addr.ll | 254 %v110 = load i8, i8* %v105, align 1, !tbaa !4
256 store i8 %v110, i8* %v111, align 1, !tbaa !4
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| D | reg-scavengebug.ll | 144 %v110 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v108, <16 x i32> %v78)
146 …%v112 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v110, i32 53…
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| D | regscavenger_fail_hwloop.ll | 135 %v110 = and i32 %v109, 256
136 %v111 = icmp ne i32 %v110, 0
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| D | expand-vstorerw-undef2.ll | 169 %v110 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v106, <32 x i32> %v109) #2
170 …%v111 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> %v110, <32 x i32> %v103, i…
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| D | reg-scav-imp-use-dbl-vec.ll | 141 %v48 = phi <32 x i32> [ %v110, %b11 ], [ undef, %b10 ]
204 %v110 = load <32 x i32>, <32 x i32>* %v109, align 128, !tbaa !3
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| D | reg-scavengebug-5.ll | 134 %v110 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v104, <16 x i32> %v86, i32 1)
151 %v127 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v121, <16 x i32> %v110)
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| /external/llvm/tools/msbuild/ |
| D | CMakeLists.txt | 24 set(VS_VERSION "v110")
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| D | install.bat | 63 REM Routine for installing v110 toolchain.
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| /external/llvm-project/llvm/test/Transforms/LoopVectorize/Hexagon/ |
| D | minimum-vf.ll | 138 %v110 = zext i8 %v109 to i16
139 %v111 = mul nsw i16 %v110, -5
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_arit.h | 166 LLVMValueRef v110,
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| /external/ppp/pppd/plugins/radius/etc/ |
| D | dictionary.ascend | 247 VALUE Ascend-Data-Svc Switched-clear-bearer-v110 39
249 VALUE Ascend-Data-Svc Switched-clear-56-v110 41
|