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/external/clang/test/CodeGen/
Dbuiltins-hexagon.c5 int v16 __attribute__((__vector_size__(64))); in foo() local
1759 __builtin_HEXAGON_V6_extractw(v16, 0); in foo()
1777 __builtin_HEXAGON_V6_pred_and_n(v16, v16); in foo()
1779 __builtin_HEXAGON_V6_pred_and(v16, v16); in foo()
1783 __builtin_HEXAGON_V6_pred_not(v16); in foo()
1789 __builtin_HEXAGON_V6_pred_or_n(v16, v16); in foo()
1791 __builtin_HEXAGON_V6_pred_or(v16, v16); in foo()
1799 __builtin_HEXAGON_V6_pred_xor(v16, v16); in foo()
1803 __builtin_HEXAGON_V6_vabsdiffh(v16, v16); in foo()
1807 __builtin_HEXAGON_V6_vabsdiffub(v16, v16); in foo()
[all …]
/external/libhevc/common/arm64/
Dihevc_intra_pred_chroma_dc.s193 dup v16.8b,w11
206 st2 {v16.8b, v17.8b}, [x2],#16
209 st2 {v16.8b, v17.8b}, [x5],#16
210 st2 {v16.8b, v17.8b}, [x8],#16
213 st2 {v16.8b, v17.8b}, [x10],#16
216 st2 {v16.8b, v17.8b}, [x2], x6
217 st2 {v16.8b, v17.8b}, [x5], x6
218 st2 {v16.8b, v17.8b}, [x8], x6
219 st2 {v16.8b, v17.8b}, [x10], x6
222 st2 {v16.8b, v17.8b}, [x2],#16
[all …]
Dihevc_deblk_luma_vert.s103 movi v16.8h, #0x2
234 mla v20.8h, v0.8h, v16.8h
286 mla v26.8h, v0.8h, v16.8h
295 umin v16.8b, v26.8b , v30.8b
299 umax v26.8b, v16.8b , v31.8b
420 uaddw v16.8h, v0.8h , v6.8b
422 rshrn v2.8b,v16.8h,#2
425 umin v16.8b, v2.8b , v27.8b
430 umax v5.8b, v16.8b , v28.8b
462 movi v16.8h, #0x3
[all …]
/external/openscreen/third_party/boringssl/ios-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S32 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
35 and v18.16b, v18.16b, v16.16b
38 and v16.16b, v16.16b, v17.16b
40 eor v5.16b, v3.16b, v16.16b // twisted H
91 ext v16.8b, v5.8b, v5.8b, #1 // A1
92 pmull v16.8h, v16.8b, v3.8b // F = A1*B
100 eor v16.16b, v16.16b, v0.16b // L = E + F
135 zip1 v20.2d, v16.2d, v17.2d
137 zip2 v21.2d, v16.2d, v17.2d
145 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/openscreen/third_party/boringssl/win-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S35 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
38 and v18.16b, v18.16b, v16.16b
41 and v16.16b, v16.16b, v17.16b
43 eor v5.16b, v3.16b, v16.16b // twisted H
98 ext v16.8b, v5.8b, v5.8b, #1 // A1
99 pmull v16.8h, v16.8b, v3.8b // F = A1*B
107 eor v16.16b, v16.16b, v0.16b // L = E + F
142 zip1 v20.2d, v16.2d, v17.2d
144 zip2 v21.2d, v16.2d, v17.2d
152 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/rust/crates/quiche/deps/boringssl/linux-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S30 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
33 and v18.16b, v18.16b, v16.16b
36 and v16.16b, v16.16b, v17.16b
38 eor v5.16b, v3.16b, v16.16b // twisted H
87 ext v16.8b, v5.8b, v5.8b, #1 // A1
88 pmull v16.8h, v16.8b, v3.8b // F = A1*B
96 eor v16.16b, v16.16b, v0.16b // L = E + F
131 zip1 v20.2d, v16.2d, v17.2d
133 zip2 v21.2d, v16.2d, v17.2d
141 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/boringssl/ios-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S32 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
35 and v18.16b, v18.16b, v16.16b
38 and v16.16b, v16.16b, v17.16b
40 eor v5.16b, v3.16b, v16.16b // twisted H
91 ext v16.8b, v5.8b, v5.8b, #1 // A1
92 pmull v16.8h, v16.8b, v3.8b // F = A1*B
100 eor v16.16b, v16.16b, v0.16b // L = E + F
135 zip1 v20.2d, v16.2d, v17.2d
137 zip2 v21.2d, v16.2d, v17.2d
145 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/openscreen/third_party/boringssl/linux-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S33 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
36 and v18.16b, v18.16b, v16.16b
39 and v16.16b, v16.16b, v17.16b
41 eor v5.16b, v3.16b, v16.16b // twisted H
92 ext v16.8b, v5.8b, v5.8b, #1 // A1
93 pmull v16.8h, v16.8b, v3.8b // F = A1*B
101 eor v16.16b, v16.16b, v0.16b // L = E + F
136 zip1 v20.2d, v16.2d, v17.2d
138 zip2 v21.2d, v16.2d, v17.2d
146 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/rust/crates/ring/pregenerated/
Dghash-neon-armv8-linux64.S30 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
33 and v18.16b, v18.16b, v16.16b
36 and v16.16b, v16.16b, v17.16b
38 eor v5.16b, v3.16b, v16.16b // twisted H
89 ext v16.8b, v5.8b, v5.8b, #1 // A1
90 pmull v16.8h, v16.8b, v3.8b // F = A1*B
98 eor v16.16b, v16.16b, v0.16b // L = E + F
133 zip1 v20.2d, v16.2d, v17.2d
135 zip2 v21.2d, v16.2d, v17.2d
143 zip1 v16.2d, v20.2d, v21.2d
[all …]
Dghash-neon-armv8-ios64.S29 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
32 and v18.16b, v18.16b, v16.16b
35 and v16.16b, v16.16b, v17.16b
37 eor v5.16b, v3.16b, v16.16b // twisted H
88 ext v16.8b, v5.8b, v5.8b, #1 // A1
89 pmull v16.8h, v16.8b, v3.8b // F = A1*B
97 eor v16.16b, v16.16b, v0.16b // L = E + F
132 zip1 v20.2d, v16.2d, v17.2d
134 zip2 v21.2d, v16.2d, v17.2d
142 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/rust/crates/quiche/deps/boringssl/ios-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S29 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
32 and v18.16b, v18.16b, v16.16b
35 and v16.16b, v16.16b, v17.16b
37 eor v5.16b, v3.16b, v16.16b // twisted H
86 ext v16.8b, v5.8b, v5.8b, #1 // A1
87 pmull v16.8h, v16.8b, v3.8b // F = A1*B
95 eor v16.16b, v16.16b, v0.16b // L = E + F
130 zip1 v20.2d, v16.2d, v17.2d
132 zip2 v21.2d, v16.2d, v17.2d
140 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/boringssl/win-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S35 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
38 and v18.16b, v18.16b, v16.16b
41 and v16.16b, v16.16b, v17.16b
43 eor v5.16b, v3.16b, v16.16b // twisted H
98 ext v16.8b, v5.8b, v5.8b, #1 // A1
99 pmull v16.8h, v16.8b, v3.8b // F = A1*B
107 eor v16.16b, v16.16b, v0.16b // L = E + F
142 zip1 v20.2d, v16.2d, v17.2d
144 zip2 v21.2d, v16.2d, v17.2d
152 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/boringssl/linux-aarch64/crypto/fipsmodule/
Dghash-neon-armv8.S33 ext v16.16b, v18.16b, v19.16b, #8 // t0=0xc2....01
36 and v18.16b, v18.16b, v16.16b
39 and v16.16b, v16.16b, v17.16b
41 eor v5.16b, v3.16b, v16.16b // twisted H
92 ext v16.8b, v5.8b, v5.8b, #1 // A1
93 pmull v16.8h, v16.8b, v3.8b // F = A1*B
101 eor v16.16b, v16.16b, v0.16b // L = E + F
136 zip1 v20.2d, v16.2d, v17.2d
138 zip2 v21.2d, v16.2d, v17.2d
146 zip1 v16.2d, v20.2d, v21.2d
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dgfx10_asm_mimg.s151 image_sample_cl v[64:66], [v32, v16], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D
152 ; GFX10: image_sample_cl v[64:66], [v32, v16], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; e…
154 image_sample_cl v[64:66], [v32, v16, v15], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
155 ; GFX10: image_sample_cl v[64:66], [v32, v16, v15], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2…
157 image_sample_cl v[64:66], [v32, v16, v15, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D
158 ; GFX10: image_sample_cl v[64:66], [v32, v16, v15, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_…
160 image_sample_cl v[64:66], [v32, v16, v15, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_CUBE
161 ; GFX10: image_sample_cl v[64:66], [v32, v16, v15, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_…
163 image_sample_cl v[64:66], [v32, v16, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D_ARRAY
164 ; GFX10: image_sample_cl v[64:66], [v32, v16, v20], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinsertelement-stack-lower.ll13 ; GCN-NEXT: v_mov_b32_e32 v16, 0x100
19 ; GCN-NEXT: v_add_u32_e32 v31, 64, v16
20 ; GCN-NEXT: v_add_u32_e32 v32, 0x44, v16
40 ; GCN-NEXT: v_add_u32_e32 v0, 4, v16
46 ; GCN-NEXT: v_add_u32_e32 v33, 0x48, v16
49 ; GCN-NEXT: v_add_u32_e32 v34, 0x4c, v16
52 ; GCN-NEXT: v_add_u32_e32 v35, 0x50, v16
55 ; GCN-NEXT: v_add_u32_e32 v36, 0x54, v16
58 ; GCN-NEXT: v_add_u32_e32 v37, 0x58, v16
61 ; GCN-NEXT: v_add_u32_e32 v38, 0x5c, v16
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-simd-ldst-multi-elem.s.cs11 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
15 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
19 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
23 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
27 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
31 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
35 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
39 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
43 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
47 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
[all …]
Dneon-simd-post-ldst-multi-elem.s.cs11 0xef,0xa5,0xc2,0x4c = ld1 {v15.8h, v16.8h}, [x15], x2
15 0xef,0xa5,0xc3,0x0c = ld1 {v15.4h, v16.4h}, [x15], x3
19 0xef,0x65,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2
23 0xef,0x65,0xc3,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3
27 0xef,0x25,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
31 0xef,0x25,0xc4,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
35 0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2
39 0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3
42 0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
46 0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
[all …]
/external/XNNPACK/src/f16-gemm/gen/
D1x8-minmax-aarch64-neonfp16arith-ld64.S35 # C v16 v18
65 FMLA v16.8h, v20.8h, v0.h[0]
67 FMLA v16.8h, v22.8h, v0.h[2]
77 FADD v16.8h, v16.8h, v18.8h
81 FMUL v16.8h, v16.8h, v4.8h
82 FMAX v16.8h, v16.8h, v5.8h
83 FMIN v16.8h, v16.8h, v6.8h
88 ST1 {v16.16b}, [x6], x14
101 FMLA v16.8h, v20.8h, v0.h[0]
109 FMLA v16.8h, v20.8h, v0.h[0]
[all …]
/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_rgba8888.s227 UADDW v16.8h, v7.8h , v30.8b ////Q8 - HAS Y + R
236 sqxtun v16.8b, v16.8h
247 ZIP1 v27.8b, v16.8b, v17.8b
248 ZIP2 v17.8b, v16.8b, v17.8b
249 mov v16.d[0], v27.d[0]
260 mov v16.d[1], v17.d[0]
263 ZIP1 v27.8h, v14.8h, v16.8h
264 ZIP2 v26.8h, v14.8h, v16.8h
272 ZIP1 v16.4s, v26.4s, v19.4s
277 ST1 {v16.4s},[x2],#16
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dssubsat.ll536 ; GFX6-NEXT: v_bfrev_b32_e32 v16, 1
539 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v16, v17, s[6:7]
546 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[6:7]
553 ; GFX6-NEXT: v_cndmask_b32_e64 v2, v16, v17, s[6:7]
560 ; GFX6-NEXT: v_cndmask_b32_e64 v3, v16, v17, s[6:7]
567 ; GFX6-NEXT: v_cndmask_b32_e64 v4, v16, v17, s[6:7]
574 ; GFX6-NEXT: v_cndmask_b32_e64 v5, v16, v17, s[6:7]
581 ; GFX6-NEXT: v_cndmask_b32_e64 v6, v16, v17, s[6:7]
588 ; GFX6-NEXT: v_cndmask_b32_e64 v7, v16, v17, s[6:7]
599 ; GFX8-NEXT: v_bfrev_b32_e32 v16, 1
[all …]
/external/XNNPACK/src/f16-gemm/gen-inc/
D1x8inc-minmax-aarch64-neonfp16arith-ld64.S36 # C v16 v18
68 FMLA v16.8h, v20.8h, v0.h[0]
70 FMLA v16.8h, v22.8h, v0.h[2]
80 FADD v16.8h, v16.8h, v18.8h
84 FMUL v16.8h, v16.8h, v4.8h
85 FMAX v16.8h, v16.8h, v5.8h
86 FMIN v16.8h, v16.8h, v6.8h
91 ST1 {v16.16b}, [x6], x14
104 FMLA v16.8h, v20.8h, v0.h[0]
112 FMLA v16.8h, v20.8h, v0.h[0]
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-simd-post-ldst-multi-elem.s38 ld1 { v15.8h, v16.8h }, [x15], x2
42 ld1 { v15.4h, v16.4h }, [x15], x3
67 ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
71 ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
96 ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
100 ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
125 ld2 { v15.8h, v16.8h }, [x15], x2
129 ld2 { v15.4h, v16.4h }, [x15], x3
151 ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
155 ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
[all …]
Dfullfp16-diagnostics.s4 fmla v0.4h, v1.4h, v16.h[3]
14 fmls v0.4h, v1.4h, v16.h[3]
24 fmul v0.4h, v1.4h, v16.h[3]
34 fmulx v0.4h, v1.4h, v16.h[3]
44 fmla h0, h1, v16.h[3]
54 fmls h0, h1, v16.h[3]
64 fmul h0, h1, v16.h[3]
74 fmulx h0, h1, v16.h[3]
/external/llvm/test/MC/AArch64/
Dneon-simd-post-ldst-multi-elem.s38 ld1 { v15.8h, v16.8h }, [x15], x2
42 ld1 { v15.4h, v16.4h }, [x15], x3
67 ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
71 ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
96 ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
100 ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
125 ld2 { v15.8h, v16.8h }, [x15], x2
129 ld2 { v15.4h, v16.4h }, [x15], x3
151 ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
155 ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
[all …]
Dfullfp16-diagnostics.s4 fmla v0.4h, v1.4h, v16.h[3]
14 fmls v0.4h, v1.4h, v16.h[3]
24 fmul v0.4h, v1.4h, v16.h[3]
34 fmulx v0.4h, v1.4h, v16.h[3]
44 fmla h0, h1, v16.h[3]
54 fmls h0, h1, v16.h[3]
64 fmul h0, h1, v16.h[3]
74 fmulx h0, h1, v16.h[3]

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