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/external/libvpx/libvpx/third_party/libyuv/source/
Drow_msa.cc78 v16i8 zero_m = {0}; \
80 vec0_m = (v8i16)__msa_ilvr_b((v16i8)in_y, (v16i8)in_y); \
81 vec1_m = (v8i16)__msa_ilvr_b((v16i8)zero_m, (v16i8)in_uv); \
128 vec0_m = (v8i16)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
129 vec1_m = (v8i16)__msa_ilvev_b((v16i8)in3, (v16i8)in2); \
154 y_out = (v16u8)__msa_pckev_b((v16i8)reg1_m, (v16i8)reg0_m); \
166 src0_m = (v16u8)__msa_ld_b((v16i8*)s, 0); \
167 src1_m = (v16u8)__msa_ld_b((v16i8*)s, 16); \
168 src2_m = (v16u8)__msa_ld_b((v16i8*)s, 32); \
169 src3_m = (v16u8)__msa_ld_b((v16i8*)s, 48); \
[all …]
Dscale_msa.cc41 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2_MSA()
42 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2_MSA()
59 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2Linear_MSA()
60 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2Linear_MSA()
79 v16i8 shuffler = {0, 4, 1, 5, 2, 6, 3, 7, 8, 12, 9, 13, 10, 14, 11, 15}; in ScaleARGBRowDown2Box_MSA()
82 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in ScaleARGBRowDown2Box_MSA()
83 src1 = (v16u8)__msa_ld_b((v16i8*)s, 16); in ScaleARGBRowDown2Box_MSA()
84 src2 = (v16u8)__msa_ld_b((v16i8*)t, 0); in ScaleARGBRowDown2Box_MSA()
85 src3 = (v16u8)__msa_ld_b((v16i8*)t, 16); in ScaleARGBRowDown2Box_MSA()
86 vec0 = (v16u8)__msa_vshf_b(shuffler, (v16i8)src0, (v16i8)src0); in ScaleARGBRowDown2Box_MSA()
[all …]
Dcompare_msa.cc34 src0 = (v16u8)__msa_ld_b((v16i8*)src_a, 0); in HammingDistance_MSA()
35 src1 = (v16u8)__msa_ld_b((v16i8*)src_a, 16); in HammingDistance_MSA()
36 src2 = (v16u8)__msa_ld_b((v16i8*)src_b, 0); in HammingDistance_MSA()
37 src3 = (v16u8)__msa_ld_b((v16i8*)src_b, 16); in HammingDistance_MSA()
63 src0 = (v16u8)__msa_ld_b((v16i8*)src_a, 0); in SumSquareError_MSA()
64 src1 = (v16u8)__msa_ld_b((v16i8*)src_a, 16); in SumSquareError_MSA()
65 src2 = (v16u8)__msa_ld_b((v16i8*)src_b, 0); in SumSquareError_MSA()
66 src3 = (v16u8)__msa_ld_b((v16i8*)src_b, 16); in SumSquareError_MSA()
67 vec0 = (v8i16)__msa_ilvr_b((v16i8)src2, (v16i8)src0); in SumSquareError_MSA()
68 vec1 = (v8i16)__msa_ilvl_b((v16i8)src2, (v16i8)src0); in SumSquareError_MSA()
[all …]
Drotate_msa.cc24 out0 = (v16u8)__msa_ilvr_b((v16i8)in1, (v16i8)in0); \
25 out1 = (v16u8)__msa_ilvl_b((v16i8)in1, (v16i8)in0); \
26 out2 = (v16u8)__msa_ilvr_b((v16i8)in3, (v16i8)in2); \
27 out3 = (v16u8)__msa_ilvl_b((v16i8)in3, (v16i8)in2); \
90 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
92 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
94 src2 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
96 src3 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
100 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
102 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
[all …]
/external/libyuv/files/source/
Dscale_msa.cc41 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2_MSA()
42 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2_MSA()
59 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2Linear_MSA()
60 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2Linear_MSA()
79 v16i8 shuffler = {0, 4, 1, 5, 2, 6, 3, 7, 8, 12, 9, 13, 10, 14, 11, 15}; in ScaleARGBRowDown2Box_MSA()
82 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in ScaleARGBRowDown2Box_MSA()
83 src1 = (v16u8)__msa_ld_b((v16i8*)s, 16); in ScaleARGBRowDown2Box_MSA()
84 src2 = (v16u8)__msa_ld_b((v16i8*)t, 0); in ScaleARGBRowDown2Box_MSA()
85 src3 = (v16u8)__msa_ld_b((v16i8*)t, 16); in ScaleARGBRowDown2Box_MSA()
86 vec0 = (v16u8)__msa_vshf_b(shuffler, (v16i8)src0, (v16i8)src0); in ScaleARGBRowDown2Box_MSA()
[all …]
Drow_msa.cc78 v16i8 zero_m = {0}; \
80 vec0_m = (v8i16)__msa_ilvr_b((v16i8)in_y, (v16i8)in_y); \
81 vec1_m = (v8i16)__msa_ilvr_b((v16i8)zero_m, (v16i8)in_uv); \
128 vec0_m = (v8i16)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
129 vec1_m = (v8i16)__msa_ilvev_b((v16i8)in3, (v16i8)in2); \
154 y_out = (v16u8)__msa_pckev_b((v16i8)reg1_m, (v16i8)reg0_m); \
174 vec0_m = (v16u8)__msa_ilvr_b((v16i8)src0_m, (v16i8)src4_m); \
175 vec1_m = (v16u8)__msa_ilvr_b((v16i8)src1_m, (v16i8)src5_m); \
176 vec2_m = (v16u8)__msa_ilvr_b((v16i8)src2_m, (v16i8)src6_m); \
177 vec3_m = (v16u8)__msa_ilvr_b((v16i8)src3_m, (v16i8)src7_m); \
[all …]
Dcompare_msa.cc34 src0 = (v16u8)__msa_ld_b((v16i8*)src_a, 0); in HammingDistance_MSA()
35 src1 = (v16u8)__msa_ld_b((v16i8*)src_a, 16); in HammingDistance_MSA()
36 src2 = (v16u8)__msa_ld_b((v16i8*)src_b, 0); in HammingDistance_MSA()
37 src3 = (v16u8)__msa_ld_b((v16i8*)src_b, 16); in HammingDistance_MSA()
63 src0 = (v16u8)__msa_ld_b((v16i8*)src_a, 0); in SumSquareError_MSA()
64 src1 = (v16u8)__msa_ld_b((v16i8*)src_a, 16); in SumSquareError_MSA()
65 src2 = (v16u8)__msa_ld_b((v16i8*)src_b, 0); in SumSquareError_MSA()
66 src3 = (v16u8)__msa_ld_b((v16i8*)src_b, 16); in SumSquareError_MSA()
67 vec0 = (v8i16)__msa_ilvr_b((v16i8)src2, (v16i8)src0); in SumSquareError_MSA()
68 vec1 = (v8i16)__msa_ilvl_b((v16i8)src2, (v16i8)src0); in SumSquareError_MSA()
[all …]
Drotate_msa.cc24 out0 = (v16u8)__msa_ilvr_b((v16i8)in1, (v16i8)in0); \
25 out1 = (v16u8)__msa_ilvl_b((v16i8)in1, (v16i8)in0); \
26 out2 = (v16u8)__msa_ilvr_b((v16i8)in3, (v16i8)in2); \
27 out3 = (v16u8)__msa_ilvl_b((v16i8)in3, (v16i8)in2); \
90 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
92 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
94 src2 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
96 src3 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
100 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
102 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvaddsplat.ll10 %v16i8 = type <16 x i8>
56 define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
57 %p = load %v16i8, %v16i8* %P
58 …%r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16,…
59 store %v16i8 %r, %v16i8* %S
67 define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
68 %p = load %v16i8, %v16i8* %P
69 …%r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -…
70 store %v16i8 %r, %v16i8* %S
126 define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dvaddsplat.ll10 %v16i8 = type <16 x i8>
56 define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
57 %p = load %v16i8, %v16i8* %P
58 …%r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16,…
59 store %v16i8 %r, %v16i8* %S
67 define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
68 %p = load %v16i8, %v16i8* %P
69 …%r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -…
70 store %v16i8 %r, %v16i8* %S
126 define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
[all …]
/external/libaom/libaom/aom_dsp/mips/
Dloopfilter_16_msa.c83 v16i8 zero = { 0 }; in aom_hz_lpf_t16_16w()
113 q0_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q0); in aom_hz_lpf_t16_16w()
132 q0_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q0); in aom_hz_lpf_t16_16w()
147 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in aom_hz_lpf_t16_16w()
153 q1_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q1); in aom_hz_lpf_t16_16w()
160 q1_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q1); in aom_hz_lpf_t16_16w()
167 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in aom_hz_lpf_t16_16w()
173 q2_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q2); in aom_hz_lpf_t16_16w()
180 q2_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q2); in aom_hz_lpf_t16_16w()
187 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in aom_hz_lpf_t16_16w()
[all …]
Dloopfilter_msa.h20 v16i8 p1_m, p0_m, q0_m, q1_m, q0_sub_p0, filt_sign; \
21 v16i8 filt, filt1, filt2, cnst4b, cnst3b; \
24 p1_m = (v16i8)__msa_xori_b(p1_in, 0x80); \
25 p0_m = (v16i8)__msa_xori_b(p0_in, 0x80); \
26 q0_m = (v16i8)__msa_xori_b(q0_in, 0x80); \
27 q1_m = (v16i8)__msa_xori_b(q1_in, 0x80); \
30 filt = filt & (v16i8)hev_in; \
36 q0_sub_p0_r = __msa_dotp_s_h((v16i8)q0_sub_p0_r, (v16i8)cnst3h); \
42 filt = __msa_pckev_b((v16i8)filt_r, (v16i8)filt_r); \
44 filt = filt & (v16i8)mask_in; \
[all …]
Dmacros_msa.h23 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
34 #define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
301 #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
316 #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
324 #define LD_SB5(...) LD_B5(v16i8, __VA_ARGS__)
331 #define LD_SB7(...) LD_B7(v16i8, __VA_ARGS__)
340 #define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__)
633 v16i8 zero_m = { 0 }; \
634 out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \
635 out1 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in1, slide_val); \
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dloopfilter_16_msa.c84 v16i8 zero = { 0 }; in hz_lpf_t16_16w()
114 q0_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q0); in hz_lpf_t16_16w()
133 q0_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q0); in hz_lpf_t16_16w()
148 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
154 q1_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q1); in hz_lpf_t16_16w()
161 q1_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q1); in hz_lpf_t16_16w()
168 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
174 q2_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q2); in hz_lpf_t16_16w()
181 q2_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q2); in hz_lpf_t16_16w()
188 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
[all …]
Dmacros_msa.h21 #define LD_SB(...) LD_V(v16i8, __VA_ARGS__)
28 #define ST_SB(...) ST_V(v16i8, __VA_ARGS__)
241 #define LD_SB2(...) LD_V2(v16i8, __VA_ARGS__)
258 #define LD_SB4(...) LD_V4(v16i8, __VA_ARGS__)
267 #define LD_SB5(...) LD_V5(v16i8, __VA_ARGS__)
274 #define LD_SB7(...) LD_V7(v16i8, __VA_ARGS__)
283 #define LD_SB8(...) LD_V8(v16i8, __VA_ARGS__)
505 v16i8 zero_m = { 0 }; \
506 out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \
507 out1 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in1, slide_val); \
[all …]
Dvpx_convolve8_msa.c29 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_4w_msa()
30 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_4w_msa()
65 out2 = (v8i16)__msa_ilvev_b((v16i8)hz_out5, (v16i8)hz_out4); in common_hv_8ht_8vt_4w_msa()
74 hz_out6 = (v8i16)__msa_sldi_b((v16i8)hz_out7, (v16i8)hz_out5, 8); in common_hv_8ht_8vt_4w_msa()
75 out3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_4w_msa()
81 hz_out8 = (v8i16)__msa_sldi_b((v16i8)hz_out9, (v16i8)hz_out7, 8); in common_hv_8ht_8vt_4w_msa()
82 out4 = (v8i16)__msa_ilvev_b((v16i8)hz_out9, (v16i8)hz_out8); in common_hv_8ht_8vt_4w_msa()
103 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_8w_msa()
104 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_8w_msa()
156 out3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_8w_msa()
[all …]
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h21 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
33 #define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
274 #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
282 #define LD_SB3(...) LD_B3(v16i8, __VA_ARGS__)
290 #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
298 #define LD_SB5(...) LD_B5(v16i8, __VA_ARGS__)
307 #define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__)
358 #define ST_SB4(...) ST_B4(v16i8, __VA_ARGS__)
514 v16i8 zero_m = { 0 }; \
516 out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \
[all …]
Dsixtap_filter_msa.c38 v16i8 vec0_m, vec1_m, vec2_m; \
55 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m; \
69 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m, vec6_m, vec7_m; \
89 tmp0 = __msa_dotp_s_h((v16i8)vec0, (v16i8)filt0); \
90 tmp0 = __msa_dpadd_s_h(tmp0, (v16i8)vec1, (v16i8)filt1); \
97 v16i8 vec0_m, vec1_m; \
112 v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \
123 v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \
138 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; in common_hz_6t_4x4_msa()
164 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; in common_hz_6t_4x8_msa()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-matmul.ll3 define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
5 ; CHECK-LABEL: smmla.v4i32.v16i8
7 …%vmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <…
11 define <4 x i32> @ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
13 ; CHECK-LABEL: ummla.v4i32.v16i8
15 …%vmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <…
19 define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
21 ; CHECK-LABEL: usmmla.v4i32.v16i8
23 …%vusmmla1.i = tail call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a…
57 define <2 x i32> @usdot_lane.v2i32.v16i8(<2 x i32> %r, <8 x i8> %a, <16 x i8> %b) {
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
[all …]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Ddenoising_msa.c116 temp2_h = (v8i16)__msa_pckev_b((v16i8)temp3_h, (v16i8)temp2_h); in vp8_denoiser_filter_msa()
117 running_avg_y = (v16u8)__msa_pckev_b((v16i8)temp1_h, (v16i8)temp0_h); in vp8_denoiser_filter_msa()
164 temp2_h = (v8i16)__msa_pckev_b((v16i8)temp3_h, (v16i8)temp2_h); in vp8_denoiser_filter_msa()
165 running_avg_y = (v16u8)__msa_pckev_b((v16i8)temp1_h, (v16i8)temp0_h); in vp8_denoiser_filter_msa()
238 running_avg_y = (v16u8)__msa_pckev_b((v16i8)adjust3, (v16i8)adjust2); in vp8_denoiser_filter_msa()
272 running_avg_y = (v16u8)__msa_pckev_b((v16i8)adjust3, (v16i8)adjust2); in vp8_denoiser_filter_msa()
331 v16i8 zero = { 0 }; in vp8_denoiser_filter_uv_msa()
338 temp0_h = (v8i16)__msa_ilvr_b(zero, (v16i8)sig0); in vp8_denoiser_filter_uv_msa()
341 temp0_h += (v8i16)__msa_ilvr_b(zero, (v16i8)sig1); in vp8_denoiser_filter_uv_msa()
344 temp0_h += (v8i16)__msa_ilvr_b(zero, (v16i8)sig2); in vp8_denoiser_filter_uv_msa()
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Darm-matmul.ll3 define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
5 ; CHECK-LABEL: smmla.v4i32.v16i8
7 …%vmmla1.i = tail call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x…
11 define <4 x i32> @ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
13 ; CHECK-LABEL: ummla.v4i32.v16i8
15 …%vmmla1.i = tail call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x…
19 define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {
21 ; CHECK-LABEL: usmmla.v4i32.v16i8
23 …%vusmmla1.i = tail call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <1…
57 define <4 x i32> @usdotq_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {
[all …]
/external/libpng/mips/
Dfilter_msa_intrinsics.c43 #define MSA_SRLI_B(a, b) __msa_srli_b((v16i8) a, b)
301 out0 = (RTYPE) __msa_ilvr_b((v16i8) in0, (v16i8) in1); \
302 out1 = (RTYPE) __msa_ilvr_b((v16i8) in2, (v16i8) in3); \
315 v16i8 zero_m = { 0 }; \
316 out0 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in0, slide_val); \
317 out1 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in1, slide_val); \
323 v16i8 zero_m = { 0 }; \
325 out2 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in2, slide_val); \
348 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \
349 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \
[all …]

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