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Searched refs:v1f64 (Results 1 – 25 of 90) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-neon-add-sub.ll164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a)
171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a)
185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b)
192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b)
199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b)
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b)
220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a)
231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>)
[all …]
Dfpconv-vector-op-scalarize-strict.ll15 …%0 = call <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i1(<1 x i1> %in, metadata !"r…
26 …%0 = call <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i1(<1 x i1> %in, metadata !"r…
32 declare <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i1(<1 x i1>, metadata, metadata)
33 declare <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i1(<1 x i1>, metadata, metadata)
Dneon-fpextend_f16.ll5 ; though the v1f64 result is legal.
23 …%val = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half> %x, metadata …
26 declare <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half>, metadata)
Darm64-vcvt.ll41 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A)
48 declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) nounwind readnone
82 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %A)
89 declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) nounwind readnone
123 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %A)
130 declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) nounwind readnone
164 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %A)
171 declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) nounwind readnone
205 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A)
212 declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) nounwind readnone
[all …]
Darm64-extract_subvector.ll45 define <1 x double> @v1f64(<2 x double> %a) nounwind {
46 ; CHECK-LABEL: v1f64:
Dvector-fcopysign.ll31 ;============ v1f64
42 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0)
52 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b)
56 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
Dvecreduce-fmax-legalization-nan.ll6 declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
35 %b = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
Dvecreduce-fmin-legalization.ll6 declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
35 %b = call nnan double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-add-sub.ll164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a)
171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a)
185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b)
192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b)
199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b)
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b)
220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a)
231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>)
[all …]
Darm64-extract_subvector.ll45 define <1 x double> @v1f64(<2 x double> %a) nounwind {
46 ; CHECK-LABEL: v1f64:
Dvector-fcopysign.ll31 ;============ v1f64
42 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0)
52 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b)
56 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c25 typedef __attribute__((vector_size(8))) double v1f64; typedef
118 v1f64 pass_v1f64(v1f64 arg) { return arg; } in pass_v1f64()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c35 typedef __attribute__((vector_size(8))) double v1f64; typedef
128 v1f64 pass_v1f64(v1f64 arg) { return arg; } in pass_v1f64()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h115 v1f64 = 60, // 1 x f64 enumerator
244 SimpleTy == MVT::v1f64); in is64BitVector()
364 case v1f64: in getVectorElementType()
425 case v1f64: return 1; in getVectorNumElements()
477 case v1f64: return 64; in getSizeInBits()
656 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2762 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2789 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2816 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2843 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2870 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2897 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2924 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2951 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2978 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2999 VT == MVT::v1f64) { in Select()
[all …]
DAArch64InstrInfo.td1434 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1577 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1738 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2059 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2152 def : Pat<(store (v1f64 FPR64:$Rt),
2249 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2355 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2409 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2591 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2619 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3200 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3227 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3254 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3281 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3308 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3335 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3362 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3389 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3416 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3437 VT == MVT::v1f64) { in Select()
[all …]
/external/llvm-project/llvm/test/Transforms/LowerMatrixIntrinsics/
Dmultiply-double-contraction-fmf.ll22 ; CHECK-NEXT: [[TMP3:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK4]], <1 x…
34 ; CHECK-NEXT: [[TMP9:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK10]], <1 …
46 ; CHECK-NEXT: [[TMP15:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK16]], <1…
58 ; CHECK-NEXT: [[TMP21:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK22]], <1…
Dmultiply-double-contraction.ll22 ; CHECK-NEXT: [[TMP3:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK4]], <1 x…
34 ; CHECK-NEXT: [[TMP9:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK10]], <1 …
46 ; CHECK-NEXT: [[TMP15:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK16]], <1…
58 ; CHECK-NEXT: [[TMP21:%.*]] = call <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[BLOCK22]], <1…
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3555 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3582 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3609 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3636 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3663 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3690 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3717 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3744 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3771 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3792 VT == MVT::v1f64) { in Select()
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-fmax.ll14 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
22 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
30 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
37 %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
82 declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>)
Dreduce-fmin.ll14 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
22 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
30 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
37 %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
82 declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)
Dreduce-fadd.ll14 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
22 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
30 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
38 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
46 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
54 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
62 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x …
69 %V1 = call double @llvm.vector.reduce.fadd.v1f64(double %arg, <1 x double> undef)
150 declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)
Dreduce-fmul.ll14 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
22 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
30 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
38 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
46 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
54 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
62 …ted cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x …
69 %V1 = call double @llvm.vector.reduce.fmul.v1f64(double %arg, <1 x double> undef)
150 declare double @llvm.vector.reduce.fmul.v1f64(double, <1 x double>)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h139 v1f64 = 84, // 1 x f64 enumerator
345 SimpleTy == MVT::v2f32 || SimpleTy == MVT::v1f64); in is64BitVector()
536 case v1f64: in getVectorElementType()
659 case v1f64: in getVectorNumElements()
744 case v1f64: return TypeSize::Fixed(64); in getSizeInBits()
1009 if (NumElements == 1) return MVT::v1f64; in getVectorVT()

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