v255 (reference) in projects: external - OpenGrok search results

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Searched refs:v255 (Results 1 – 25 of 76) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
D	gfx7_unsupported.s	`7 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095 10 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095 91 ds_read_addtid_b32 v255 offset:65535 94 ds_read_i8_d16 v255, v1 offset:65535 97 ds_read_i8_d16_hi v255, v1 offset:65535 100 ds_read_u16_d16 v255, v1 offset:65535 103 ds_read_u16_d16_hi v255, v1 offset:65535 106 ds_read_u8_d16 v255, v1 offset:65535 109 ds_read_u8_d16_hi v255, v1 offset:65535 112 ds_write_addtid_b32 v255 offset:65535 [all …]`
D	gfx10_unsupported.s	8 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095 11 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095 65 v_add_i16 v255, v1, v2 80 v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 83 v_add_u16_e64 v255, v1, v2 92 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 107 v_addc_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 113 v_addc_co_u32_e64 v255, s[12:13], v1, v2, s[6:7] 122 v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 134 v_ashr_i32 v255, v1, v2 [all …]
D	gfx9_unsupported.s	`7 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095 28 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095 157 v_add_co_ci_u32_e32 v255, vcc, v1, v2, vcc 160 v_add_co_ci_u32_e64 v255, s12, v1, v2, s6 166 v_add_nc_i16 v255, v1, v2 169 v_add_nc_i32 v255, v1, v2 172 v_add_nc_u16 v255, v1, v2 178 v_add_nc_u32_e32 v255, v1, v2 181 v_add_nc_u32_e64 v255, v1, v2 184 v_add_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD [all …]`
D	gfx8_unsupported.s	`7 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095 28 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095 67 ds_read_addtid_b32 v255 offset:65535 70 ds_read_i8_d16 v255, v1 offset:65535 73 ds_read_i8_d16_hi v255, v1 offset:65535 76 ds_read_u16_d16 v255, v1 offset:65535 79 ds_read_u16_d16_hi v255, v1 offset:65535 82 ds_read_u8_d16 v255, v1 offset:65535 85 ds_read_u8_d16_hi v255, v1 offset:65535 88 ds_write_addtid_b32 v255 offset:65535 [all …]`
D	gfx10_asm_all.s	`13 ds_add_u32 v255, v254 19 ds_add_u32 v255, v1 25 ds_add_u32 v255, v254 offset:0 31 ds_add_u32 v255, v1 offset:0 37 ds_add_u32 v255, v254 offset:4660 43 ds_add_u32 v255, v1 offset:4660 49 ds_add_u32 v255, v254 offset:65535 55 ds_add_u32 v255, v1 offset:65535 61 ds_add_u32 v255, v254 gds 67 ds_add_u32 v255, v1 gds [all …]`
D	xdl-insts-gfx908.s	7 v_dot2c_f32_f16 v255, v1, v2 13 v_dot2c_f32_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 16 v_dot2c_f32_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 19 v_dot2c_f32_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 109 v_dot2c_i32_i16 v255, v1, v2 115 v_dot2c_i32_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 118 v_dot2c_i32_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 121 v_dot2c_i32_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 199 v_dot4c_i32_i8 v255, v1, v2 205 v_dot4c_i32_i8_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 [all …]
D	xdl-insts-gfx1011-gfx1012.s	7 v_dot2c_f32_f16_e32 v255, v1, v2 13 v_dot2c_f32_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 16 v_dot2c_f32_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 19 v_dot2c_f32_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 91 v_dot4c_i32_i8_e32 v255, v1, v2 97 v_dot4c_i32_i8_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 100 v_dot4c_i32_i8_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 103 v_dot4c_i32_i8_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
D	gfx9_asm_all.s	`8 ds_add_u32 v255, v2 offset:65535 11 ds_add_u32 v1, v255 offset:65535 29 ds_sub_u32 v255, v2 offset:65535 32 ds_sub_u32 v1, v255 offset:65535 50 ds_rsub_u32 v255, v2 offset:65535 53 ds_rsub_u32 v1, v255 offset:65535 71 ds_inc_u32 v255, v2 offset:65535 74 ds_inc_u32 v1, v255 offset:65535 92 ds_dec_u32 v255, v2 offset:65535 95 ds_dec_u32 v1, v255 offset:65535 [all …]`
D	gfx8_asm_all.s	`7 ds_add_u32 v255, v2 offset:65535 10 ds_add_u32 v1, v255 offset:65535 28 ds_sub_u32 v255, v2 offset:65535 31 ds_sub_u32 v1, v255 offset:65535 49 ds_rsub_u32 v255, v2 offset:65535 52 ds_rsub_u32 v1, v255 offset:65535 70 ds_inc_u32 v255, v2 offset:65535 73 ds_inc_u32 v1, v255 offset:65535 91 ds_dec_u32 v255, v2 offset:65535 94 ds_dec_u32 v1, v255 offset:65535 [all …]`
D	gfx7_asm_all.s	`6 ds_add_u32 v255, v2 offset:65535 9 ds_add_u32 v1, v255 offset:65535 27 ds_sub_u32 v255, v2 offset:65535 30 ds_sub_u32 v1, v255 offset:65535 48 ds_rsub_u32 v255, v2 offset:65535 51 ds_rsub_u32 v1, v255 offset:65535 69 ds_inc_u32 v255, v2 offset:65535 72 ds_inc_u32 v1, v255 offset:65535 90 ds_dec_u32 v255, v2 offset:65535 93 ds_dec_u32 v1, v255 offset:65535 [all …]`
D	gfx10_asm_mimg.s	33 image_load v255, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D glc 34 ; GFX10: image_load v255, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x00,0… 39 image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 40 ; GFX10: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x00,0… 43 image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 44 ; GFX10: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,… 70 image_load_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D 71 ; GFX10: image_load_mip v[253:255], [v255, v254], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D ; encoding: [… 73 image_load_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D 74 ; GFX10: image_load_mip v[254:255], [v254, v255, v253], s[0:7] dmask:0xc dim:SQ_RSRC_IMG_2D ; encod… [all …]
D	mimg-err.s	`44 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 47 image_atomic_add v[6:7], v255, s[8:15] dmask:0xf 56 image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 tfe`
D	atomic-fadd-insts.s	`7 buffer_atomic_add_f32 v255, off, s[8:11], s3 offset:4095 52 buffer_atomic_pk_add_f16 v255, off, s[8:11], s3 offset:4095 97 global_atomic_add_f32 v[1:2], v255, off offset:-1 106 global_atomic_pk_add_f16 v[1:2], v255, off offset:-1`
D	gfx1030_unsupported.s	`8 v_fmac_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 15 v_fmac_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWO…`
D	vop1-gfx9.s	`31 v_sat_pk_u8_i16 v255, v1 43 v_screen_partition_4se_b32 v5, v255`
D	vopc.s	`25 v_cmp_lt_f32 vcc, v255, v255`
D	dl-insts.s	`11 v_fmac_f32 v255, v1, v2 13 v_fmac_f32 v5, v255, v2 45 v_fmac_f32 v5, v1, v255 50 v_fmac_f32_e64 v255, v1, v2 52 v_fmac_f32_e64 v5, v255, v2 80 v_fmac_f32_e64 v5, v1, v255 131 v_fmac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 133 v_fmac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 135 v_fmac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 196 v_xnor_b32 v255, v1, v2 [all …]`
D	mubuf-gfx9.s	`60 buffer_store_format_d16_hi_x v255, off, s[12:15], s4 64 buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095`
D	vop3-errs.s	`76 v_interp_p2_f32_e64 v255, v2, attr0.x high 80 v_interp_p2_f32_e64 v255, v2, attr0.x v0`
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
D	flat_gfx10.txt	7 # CHECK: scratch_load_dword v1, v255, off offset:-1 glc dlc ; encoding: [0xff,0x5f,0x31,0xdc,0xff,0… 10 # CHECK: scratch_load_dword v5, v255, off offset:-1 glc slc ; encoding: [0xff,0x4f,0x33,0xdc,0xff,0… 16 # CHECK: scratch_load_dword v255, off, s105 offset:2047 dlc ; encoding: [0xff,0x57,0x30,0xdc,0x00,0… 19 # CHECK: scratch_load_dword v255, v2, off ; encoding: [0x00,0x40,0x30,0xdc,0x02,0x00,0x7d,0xff] 28 # CHECK: scratch_load_dword v5, v255, off slc dlc ; encoding: [0x00,0x50,0x32,0xdc,0xff,0x00,0x7d,0… 31 # CHECK: scratch_load_dword v255, off, s2 offset:1 ; encoding: [0x01,0x40,0x30,0xdc,0x00,0x00,0x02,… 41 # CHECK: scratch_store_dword off, v255, s3 offset:-1 ; encoding: [0xff,0x4f,0x70,0xdc,0x00,0xff,0x0…
D	xdl-insts-gfx908.txt	6 # CHECK: v_dot2c_f32_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x6f] 12 # CHECK: v_dot2c_f32_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 15 # CHECK: v_dot2c_f32_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 18 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 102 # CHECK: v_dot2c_i32_i16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x71] 108 # CHECK: v_dot2c_i32_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 111 # CHECK: v_dot2c_i32_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 114 # CHECK: v_dot2c_i32_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding… 186 # CHECK: v_dot4c_i32_i8_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x73] 192 # CHECK: v_dot4c_i32_i8_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding:… [all …]
D	vopc_vi.txt	`12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]`
/external/llvm/test/MC/AMDGPU/
D	vopc.s	`25 v_cmp_lt_f32 vcc, v255, v255`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	reserve-vgpr-for-sgpr-spill.ll	`9 ; GCN: buffer_store_dword v255, off, s[0:3], s32 10 ; GCN: v_writelane_b32 v255, s33, 2 11 ; GCN: v_writelane_b32 v255, s30, 0 12 ; GCN: v_writelane_b32 v255, s31, 1 14 ; GCN: v_readlane_b32 s30, v255, 0 15 ; GCN: v_readlane_b32 s31, v255, 1 16 ; GCN: v_readlane_b32 s33, v255, 2 100 ; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32 151 ; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32`
/external/webp/src/dsp/
D	upsampling_neon.c	`82 #define v255 vdup_n_u8(255) macro 98 INIT_VECTOR4(r_g_b_v255, r, g, b, v255); \ 104 INIT_VECTOR4(b_g_r_v255, b, g, r, v255); \ 110 INIT_VECTOR4(v255_r_g_b, v255, r, g, b); \ 122 const uint8x8_t ba = vsri_n_u8(b, v255, 4); /* shift a, insert b */ \`

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