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/external/libxaac/decoder/armv8/
Dixheaacd_sbr_qmfsyn64_winadd.s82 mov v26.16b, v20.16b
85 sMLAL v26.4s, v0.4h, v1.4h
89 sMLAL v26.4s, v2.4h, v3.4h
94 sMLAL v26.4s, v5.4h, v4.4h
99 sMLAL v26.4s, v7.4h, v6.4h
107 sMLAL v26.4s, v9.4h, v8.4h
119 sMLAL v26.4s, v10.4h, v11.4h
123 sMLAL v26.4s, v12.4h, v13.4h
128 sMLAL v26.4s, v15.4h, v14.4h
133 sMLAL v26.4s, v17.4h, v16.4h
[all …]
Dixheaacd_post_twiddle_overlap.s355 UZP1 v26.8h, v6.8h, v6.8h
357 MOV v6.d[0], v26.d[0]
360 uMULL v26.4s, v0.4h, v8.4h
394 ushR v26.4s, v26.4s, #16
399 sMLAL v26.4s, v1.4h, v8.4h
409 SUB v28.4s, v24.4s , v26.4s
412 mov v26.16b, v30.16b
425 UZP1 v19.8h, v26.8h, v26.8h
426 UZP2 v21.8h, v26.8h, v26.8h
427 MOV v26.d[0], v19.d[0]
[all …]
/external/libavc/common/armv8/
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s82 movi v26.8h, #0x14 // Filter coeff 20 into Q13
120 uaddl v26.8h, v3.8b, v9.8b
125 mls v20.8h, v26.8h , v30.8h
126 uaddl v26.8h, v13.8b, v16.8b
128 mls v22.8h, v26.8h , v30.8h
131 ext v26.16b, v18.16b , v20.16b , #6
134 add v0.8h, v24.8h , v26.8h
136 ext v26.16b, v18.16b , v20.16b , #8
137 add v24.8h, v24.8h , v26.8h
139 saddl v26.4s, v18.4h, v23.4h
[all …]
Dih264_intra_pred_luma_16x16_av8.s502 shl v26.8h, v6.8h, #3
504 sub v30.8h, v30.8h , v26.8h
506 add v26.8h, v28.8h , v0.8h
508 sqrshrun v20.8b, v26.8h, #5
510 add v26.8h, v26.8h , v6.8h
512 sqrshrun v22.8b, v26.8h, #5
515 add v26.8h, v26.8h , v6.8h
517 sqrshrun v20.8b, v26.8h, #5
520 add v26.8h, v26.8h , v6.8h
522 sqrshrun v22.8b, v26.8h, #5
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s143 movi v26.8h, #0x14 // Filter coeff 20 into Q13
182 uaddl v26.8h, v3.8b, v9.8b
187 mls v20.8h, v26.8h , v30.8h
188 uaddl v26.8h, v13.8b, v16.8b
190 mls v22.8h, v26.8h , v30.8h
194 ext v26.16b, v18.16b , v20.16b , #6
197 add v0.8h, v24.8h , v26.8h
199 ext v26.16b, v18.16b , v20.16b , #8
200 add v24.8h, v24.8h , v26.8h
202 saddl v26.4s, v18.4h, v22.4h
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-min-01.ll8 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-02.ll8 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-03.ll8 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-04.ll8 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-03.ll8 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-04.ll8 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-01.ll8 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-02.ll8 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
Dvec-move-01.ll8 ; CHECK: vlr %v24, %v26
16 ; CHECK: vlr %v24, %v26
24 ; CHECK: vlr %v24, %v26
32 ; CHECK: vlr %v24, %v26
40 ; CHECK: vlr %v24, %v26
48 ; CHECK: vlr %v24, %v26
56 ; CHECK: vlr %v24, %v26
64 ; CHECK: vlr %v24, %v26
72 ; CHECK: vlr %v24, %v26
80 ; CHECK: vlr %v24, %v26
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-min-02.ll8 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-03.ll8 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-03.ll8 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-01.ll8 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-02.ll8 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-04.ll8 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}}
Dvec-min-01.ll8 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}}
Dvec-max-04.ll8 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
18 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
28 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
38 ; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}}
48 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
58 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
68 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
78 ; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}}
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1.s155 …Uxtl v26.8h, v18.8b //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
198 …SADDW v26.8h, v26.8h , v24.8b //II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val…
204 …SMAX v26.8h, v26.8h , v2.8h //II pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.va…
205 …UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
211 xtn v30.8b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[0])
234 …Uxtl v26.8h, v3.8b //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(…
235 …SADDW v26.8h, v26.8h , v24.8b //pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0]…
236 …SMAX v26.8h, v26.8h , v2.8h //pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val[0…
237 …UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
245 xtn v30.8b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[0])
[all …]
Dihevc_inter_pred_chroma_vert_w16inp.s213 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
215 smlal v26.4s, v3.4h, v17.4h
216 smlal v26.4s, v4.4h, v18.4h
218 smlal v26.4s, v5.4h, v19.4h
234 sqshrn v26.4h, v26.4s,#6 //right shift
249 sqrshrun v26.8b, v26.8h,#6 //rounding shift
256 st1 {v26.s}[0],[x9],x3 //stores the loaded value
266 smull v26.4s, v2.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
268 smlal v26.4s, v3.4h, v17.4h
271 smlal v26.4s, v4.4h, v18.4h
[all …]
/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s117 ext v26.8b, v7.8b , v7.8b , #5
121 uaddl v18.8h, v26.8b, v7.8b //// a0 + a5 (column3,row1)
130 ext v26.8b, v7.8b , v7.8b , #2
134 umlal v18.8h, v26.8b, v1.8b //// a0 + a5 + 20a2 (column3,row1)
143 ext v26.8b, v7.8b , v7.8b , #3
147 umlal v18.8h, v26.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column3,row1)
156 ext v26.8b, v7.8b , v7.8b , #1
160 umlsl v18.8h, v26.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column3,row1)
169 ext v26.8b, v7.8b , v7.8b , #4
172 umlsl v18.8h, v26.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column3,row1)
[all …]

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