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/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_rgba8888.s183 UZP1 v27.8b, v2.8b, v3.8b
185 mov v2.d[0], v27.d[0]
244 ZIP1 v27.8b, v14.8b, v15.8b
246 mov v14.d[0], v27.d[0]
247 ZIP1 v27.8b, v16.8b, v17.8b
249 mov v16.d[0], v27.d[0]
251 ZIP1 v27.8b, v20.8b, v21.8b
253 mov v20.d[0], v27.d[0]
254 ZIP1 v27.8b, v22.8b, v23.8b
256 mov v22.d[0], v27.d[0]
[all …]
/external/fec/
Dviterbi27_mmx.c20 struct v27 { struct
30 struct v27 *vp = (struct v27 *)p; in init_viterbi27_mmx() argument
66 struct v27 *vp; in create_viterbi27_mmx()
72 if((vp = (struct v27 *)malloc(sizeof(struct v27))) == NULL) in create_viterbi27_mmx()
90 struct v27 *vp = (struct v27 *)p; in chainback_viterbi27_mmx()
109 struct v27 *vp = p; in delete_viterbi27_mmx()
Dviterbi27_sse.c18 struct v27 { struct
28 struct v27 *vp; in create_viterbi27_sse() argument
35 if((vp = malloc(sizeof(struct v27))) == NULL) in create_viterbi27_sse()
57 struct v27 *vp = p; in init_viterbi27_sse()
78 struct v27 *vp = p; in chainback_viterbi27_sse()
107 struct v27 *vp = p; in delete_viterbi27_sse()
Dviterbi27_sse2.c18 struct v27 { struct
28 struct v27 *vp = p; in init_viterbi27_sse2() argument
57 struct v27 *vp; in create_viterbi27_sse2()
64 if(posix_memalign(&p, sizeof(__m128i),sizeof(struct v27))) in create_viterbi27_sse2()
66 vp = (struct v27 *)p; in create_viterbi27_sse2()
84 struct v27 *vp = p; in chainback_viterbi27_sse2()
112 struct v27 *vp = p; in delete_viterbi27_sse2()
124 struct v27 *vp = p;
Dviterbi27_port.c20 struct v27 { struct
30 struct v27 *vp = p; in init_viterbi27_port() argument
57 struct v27 *vp; in create_viterbi27_port()
63 if((vp = malloc(sizeof(struct v27))) == NULL) in create_viterbi27_port()
80 struct v27 *vp = p; in chainback_viterbi27_port()
108 struct v27 *vp = p; in delete_viterbi27_port()
137 struct v27 *vp = p; in update_viterbi27_blk_port()
Dviterbi27_av.c18 struct v27 { struct
28 struct v27 *vp = p; in init_viterbi27_av() argument
54 struct v27 *vp; in create_viterbi27_av()
60 if((vp = (struct v27 *)malloc(sizeof(struct v27))) == NULL) in create_viterbi27_av()
76 struct v27 *vp = p; in chainback_viterbi27_av()
104 struct v27 *vp = p; in delete_viterbi27_av()
114 struct v27 *vp = p; in update_viterbi27_blk_av()
/external/libavc/common/armv8/
Dih264_inter_pred_filters_luma_horz_av8.s138 ext v27.8b, v6.8b , v7.8b, #5 ////extract a[5] (column2,row1)
141 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
146 ext v27.8b, v6.8b , v7.8b, #2 ////extract a[2] (column2,row1)
149 umlal v16.8h, v27.8b, v1.8b //// a0 + a5 + 20a2 (column2,row1)
154 ext v27.8b, v6.8b , v7.8b, #3 ////extract a[3] (column2,row1)
157 umlal v16.8h, v27.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column2,row1)
162 ext v27.8b, v6.8b , v7.8b, #1 ////extract a[1] (column2,row1)
165 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1)
170 ext v27.8b, v6.8b , v7.8b, #4 ////extract a[4] (column2,row1)
173 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row1)
[all …]
Dih264_inter_pred_luma_horz_qpel_av8.s146 ext v27.8b, v6.8b , v7.8b , #5
149 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
154 ext v27.8b, v6.8b , v7.8b , #2
157 umlal v16.8h, v27.8b, v1.8b //// a0 + a5 + 20a2 (column2,row1)
162 ext v27.8b, v6.8b , v7.8b , #3
165 umlal v16.8h, v27.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column2,row1)
170 ext v27.8b, v6.8b , v7.8b , #1
173 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1)
178 ext v27.8b, v6.8b , v7.8b , #4
181 umlsl v16.8h, v27.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row1)
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-compare-instructions.s.cs6 0x7d,0x8f,0xbc,0x2e = cmeq v29.2s, v27.2s, v28.2s
13 0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s
20 0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s
27 0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s
34 0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s
41 0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s
48 0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s
55 0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s
62 0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s
69 0x7d,0x8f,0xbc,0x0e = cmtst v29.2s, v27.2s, v28.2s
[all …]
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1_chroma.s202 UZP1 v27.8b, v5.8b, v17.8b
204 mov v5.8b,v27.8b
211 ZIP1 v27.8b, v5.8b, v17.8b
213 mov v5.8b,v27.8b
223 UZP1 v27.8b, v22.8b, v23.8b
225 mov v22.8b,v27.8b
236 ZIP1 v27.8b, v24.8b, v25.8b
238 mov v24.8b,v27.8b
284 UZP1 v27.8b, v22.8b, v23.8b
286 mov v22.8b,v27.8b
[all …]
Dihevc_intra_pred_luma_planar.s179 dup v27.8h,w4 //(1)
184 umlal v27.8h, v5.8b, v0.8b //(1)(row+1) * src[nt-1]
187 umlal v27.8h, v17.8b, v1.8b //(1)(col+1) * src[3nt+1]
190 umlal v27.8h, v6.8b, v3.8b //(1)(nt-1-row) * src[2nt+1+col]
193 umlal v27.8h, v19.8b, v20.8b //(1)(nt-1-col) * src[2nt-1-row]
209 sshl v27.8h, v27.8h, v29.8h //(1)shr
214 xtn v27.8b, v27.8h //(1)
223 st1 {v27.8b},[x2], x3 //(1)str 8 values
333 dup v27.8h,w4 //(1n)(1)
351 umlal v27.8h, v5.8b, v0.8b //(1)(row+1) * src[nt-1]
[all …]
Dihevc_inter_pred_chroma_horz_w16out.s140 dup v27.8b, v2.b[3] //coeffabs_3 = vdup_lane_u8(coeffabs, 3)
220 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
235 umlsl v28.8h, v7.8b, v27.8b
282 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
299 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
315 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
331 umlsl v28.8h, v7.8b, v27.8b
359 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
381 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
395 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
[all …]
Dihevc_inter_pred_chroma_horz.s140 dup v27.8b, v2.b[3] //coeffabs_3 = vdup_lane_u8(coeffabs, 3)
205 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
217 umlsl v28.8h, v7.8b, v27.8b
272 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
292 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
313 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
331 umlsl v28.8h, v7.8b, v27.8b
364 umlsl v22.8h, v14.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
384 umlsl v20.8h, v15.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
398 umlsl v30.8h, v6.8b, v27.8b //mul_res = vmlal_u8(src[0_1], coeffabs_1)//
[all …]
Dihevc_itrans_recon_8x8.s421 trn1 v27.4h, v3.4h, v7.4h
426 trn1 v2.2s, v25.2s, v27.2s
427 trn2 v3.2s, v25.2s, v27.2s ////x0,x1,x2,x3 first qudrant transposing continued.....
433 trn1 v27.4h, v11.4h, v15.4h
436 trn1 v10.2s, v25.2s, v27.2s
437 trn2 v11.2s, v25.2s, v27.2s ////x4,x5,x6,x7 third qudrant transposing continued.....
500 trn1 v27.4h, v2.4h, v3.4h
505 trn1 v2.2s, v27.2s, v25.2s
506 trn2 v4.2s, v27.2s, v25.2s
510 trn1 v27.4h, v6.4h, v7.4h
[all …]
/external/llvm/test/MC/Hexagon/
Dv60-alu.s32 #CHECK: 1cb8cada { v27:26.w = vsub(v10.uh,{{ *}}v24.uh) }
33 v27:26.w=vsub(v10.uh,v24.uh)
35 #CHECK: 1cbcdbe8 { v9:8.w = vsub(v27.h,{{ *}}v28.h) }
36 v9:8.w=vsub(v27.h,v28.h)
80 #CHECK: 1c7ad4a6 { v7:6.h = vadd(v21:20.h,{{ *}}v27:26.h) }
81 v7:6.h=vadd(v21:20.h,v27:26.h)
98 #CHECK: 1c86dace { v15:14.ub = vsub(v27:26.ub,{{ *}}v7:6.ub):sat }
99 v15:14.ub=vsub(v27:26.ub,v7:6.ub):sat
122 #CHECK: 1c88da56 { v23:22.w = vadd(v27:26.w,{{ *}}v9:8.w):sat }
123 v23:22.w=vadd(v27:26.w,v9:8.w):sat
[all …]
/external/llvm-project/llvm/test/MC/Hexagon/
Dv60-alu.s32 #CHECK: 1cb8cada { v27:26.w = vsub(v10.uh,{{ *}}v24.uh) }
33 v27:26.w=vsub(v10.uh,v24.uh)
35 #CHECK: 1cbcdbe8 { v9:8.w = vsub(v27.h,{{ *}}v28.h) }
36 v9:8.w=vsub(v27.h,v28.h)
80 #CHECK: 1c7ad4a6 { v7:6.h = vadd(v21:20.h,{{ *}}v27:26.h) }
81 v7:6.h=vadd(v21:20.h,v27:26.h)
98 #CHECK: 1c86dace { v15:14.ub = vsub(v27:26.ub,{{ *}}v7:6.ub):sat }
99 v15:14.ub=vsub(v27:26.ub,v7:6.ub):sat
122 #CHECK: 1c88da56 { v23:22.w = vadd(v27:26.w,{{ *}}v9:8.w):sat }
123 v23:22.w=vadd(v27:26.w,v9:8.w):sat
[all …]
/external/llvm/test/MC/AArch64/
Dneon-compare-instructions.s13 cmeq v29.2s, v27.2s, v28.2s
35 cmhs v29.2s, v27.2s, v28.2s
43 cmls v29.2s, v28.2s, v27.2s
72 cmge v29.2s, v27.2s, v28.2s
80 cmle v29.2s, v28.2s, v27.2s
109 cmhi v29.2s, v27.2s, v28.2s
117 cmlo v29.2s, v28.2s, v27.2s
146 cmgt v29.2s, v27.2s, v28.2s
154 cmlt v29.2s, v28.2s, v27.2s
181 cmtst v29.2s, v27.2s, v28.2s
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-compare-instructions.s13 cmeq v29.2s, v27.2s, v28.2s
35 cmhs v29.2s, v27.2s, v28.2s
43 cmls v29.2s, v28.2s, v27.2s
72 cmge v29.2s, v27.2s, v28.2s
80 cmle v29.2s, v28.2s, v27.2s
109 cmhi v29.2s, v27.2s, v28.2s
117 cmlo v29.2s, v28.2s, v27.2s
146 cmgt v29.2s, v27.2s, v28.2s
154 cmlt v29.2s, v28.2s, v27.2s
181 cmtst v29.2s, v27.2s, v28.2s
[all …]
/external/libavc/encoder/armv8/
Dih264e_evaluate_intra_chroma_modes_av8.s193 ld1 {v27.8h}, [x1]
195 dup v20.8h, v27.h[7] ///HORIZONTAL VALUE ROW=0//
196 dup v21.8h, v27.h[7]
218 dup v20.8h, v27.h[6]
219 dup v21.8h, v27.h[6] ///HORIZONTAL VALUE ROW=1//
235 dup v20.8h, v27.h[5]
236 dup v21.8h, v27.h[5] ///HORIZONTAL VALUE ROW=2//
251 dup v20.8h, v27.h[4]
252 dup v21.8h, v27.h[4] ///HORIZONTAL VALUE ROW=3//
270 dup v20.8h, v27.h[3]
[all …]
/external/XNNPACK/src/f16-gemm/gen/
D8x8-minmax-aarch64-neonfp16arith-ld64.S59 # C v27
129 MOV v27.16b, v24.16b
156 FMLA v27.8h, v16.8h, v3.h[0]
167 FMLA v27.8h, v17.8h, v3.h[1]
176 FMLA v27.8h, v18.8h, v3.h[2]
185 FMLA v27.8h, v19.8h, v3.h[3]
201 FMUL v27.8h, v27.8h, v20.8h
211 FMAX v27.8h, v27.8h, v21.8h
220 FMIN v27.8h, v27.8h, v22.8h
235 ST1 {v27.16b}, [x14], x0
[all …]
/external/XNNPACK/src/f16-gemm/gen-inc/
D8x8inc-minmax-aarch64-neonfp16arith-ld64.S60 # C v27
153 FMLA v27.8h, v16.8h, v3.h[0]
164 FMLA v27.8h, v17.8h, v3.h[1]
173 FMLA v27.8h, v18.8h, v3.h[2]
182 FMLA v27.8h, v19.8h, v3.h[3]
198 FMUL v27.8h, v27.8h, v20.8h
208 FMAX v27.8h, v27.8h, v21.8h
217 FMIN v27.8h, v27.8h, v22.8h
234 ST1 {v27.16b}, [x14], x0
268 FMLA v27.8h, v16.8h, v3.h[0]
[all …]
/external/XNNPACK/src/f16-gemm/
D8x8-aarch64-neonfp16arith-ld64.S.in59 # C v27
140 MOV v27.16b, v24.16b
167 FMLA v27.8h, v16.8h, v3.h[0]
178 FMLA v27.8h, v17.8h, v3.h[1]
187 FMLA v27.8h, v18.8h, v3.h[2]
196 FMLA v27.8h, v19.8h, v3.h[3]
212 FMUL v27.8h, v27.8h, v20.8h
222 FMAX v27.8h, v27.8h, v21.8h
231 FMIN v27.8h, v27.8h, v22.8h
249 ST1 {v27.16b}, [x14], x0
[all …]
/external/XNNPACK/src/qs8-gemm/
D4x16c4-aarch64-neondot-ld32.S31 # C3 x7 v19 v23 v27 v31
72 MOV v27.16b, v24.16b
100 SDOT v27.4s, v6.16b, v3.4b[0]
144 BIC v7.16b, v27.16b, v2.16b
149 SQRDMULH v27.4s, v27.4s, v0.4s
154 SSRA v27.4s, v7.4s, 31
182 SRSHL v27.4s, v27.4s, v1.4s
195 SQXTN v27.4h, v27.4s
205 SQXTN2 v27.8h, v31.4s
214 SQADD v27.8h, v27.8h, v2.8h
[all …]
/external/XNNPACK/src/f32-igemm/gen/
D5x8-minmax-aarch64-neonfma-cortex-a57.S59 # C v26 v27
104 MOV v27.16b, v21.16b
163 FMLA v27.4s, v13.4s, v6.s[0]
177 FMLA v27.4s, v15.4s, v6.s[1]
191 FMLA v27.4s, v17.4s, v6.s[2]
204 FMLA v27.4s, v19.4s, v6.s[3]
219 FMLA v27.4s, v13.4s, v7.s[0]
234 FMLA v27.4s, v15.4s, v7.s[1]
246 FMLA v27.4s, v17.4s, v7.s[2]
259 FMLA v27.4s, v19.4s, v7.s[3]
[all …]
D5x8-minmax-aarch64-neonfma-cortex-a75.S59 # C v26 v27
106 MOV v27.16b, v21.16b
169 FMLA v27.4s, v13.4s, v6.s[0]
183 FMLA v27.4s, v15.4s, v6.s[1]
197 FMLA v27.4s, v17.4s, v6.s[2]
210 FMLA v27.4s, v19.4s, v6.s[3]
225 FMLA v27.4s, v13.4s, v7.s[0]
240 FMLA v27.4s, v15.4s, v7.s[1]
252 FMLA v27.4s, v17.4s, v7.s[2]
265 FMLA v27.4s, v19.4s, v7.s[3]
[all …]

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