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/external/llvm/test/MC/SystemZ/
Dinsn-good-z13.s22 #CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
23 #CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
24 #CHECK: vab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
28 vab %v0, %v0, %v31
29 vab %v0, %v31, %v0
30 vab %v31, %v0, %v0
34 #CHECK: vaccb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf1]
35 #CHECK: vaccb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf1]
36 #CHECK: vaccb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf1]
40 vaccb %v0, %v0, %v31
[all …]
/external/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z13.txt20 #CHECK: vab %v31, %v31, %v31
29 #CHECK: vaccb %v31, %v31, %v31
38 #CHECK: vacccq %v31, %v31, %v31, %v31
47 #CHECK: vaccf %v31, %v31, %v31
56 #CHECK: vaccg %v31, %v31, %v31
65 #CHECK: vacch %v31, %v31, %v31
74 #CHECK: vaccq %v31, %v31, %v31
83 #CHECK: vacq %v31, %v31, %v31, %v31
92 #CHECK: vaf %v31, %v31, %v31
101 #CHECK: vag %v31, %v31, %v31
[all …]
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-good-z14.s440 #CHECK: vap %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x71]
441 #CHECK: vap %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x71]
442 #CHECK: vap %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x71]
448 vap %v0, %v0, %v31, 0, 0
449 vap %v0, %v31, %v0, 0, 0
450 vap %v31, %v0, %v0, 0, 0
455 #CHECK: vbperm %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x85]
457 #CHECK: vbperm %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x85]
459 #CHECK: vbperm %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x85]
464 vbperm %v0, %v0, %v31
[all …]
Dinsn-good-z13.s451 #CHECK: va %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
452 #CHECK: va %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
453 #CHECK: va %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
458 va %v0, %v0, %v31, 0
459 va %v0, %v31, %v0, 0
460 va %v31, %v0, %v0, 0
464 #CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
465 #CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
466 #CHECK: vab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
470 vab %v0, %v0, %v31
[all …]
Dinsn-good-z15.s32 #CHECK: vllebrzg %v31, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
39 #CHECK: vllebrzg %v31, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
47 ldrv %v31, 0
63 #CHECK: vllebrze %v31, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x68,0x04]
71 lerv %v31, 0
413 #CHECK: vstebrg %v31, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0a]
421 stdrv %v31, 0
429 #CHECK: vstebrf %v31, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0b]
437 sterv %v31, 0
444 #CHECK: vcefb %v0, %v31, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc3]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z13.txt548 # CHECK: va %v31, %v31, %v31, 11
557 # CHECK: vab %v31, %v31, %v31
566 # CHECK: vac %v31, %v31, %v31, %v31, 11
575 # CHECK: vacc %v31, %v31, %v31, 11
584 # CHECK: vaccb %v31, %v31, %v31
593 # CHECK: vaccc %v31, %v31, %v31, %v31, 11
602 # CHECK: vacccq %v31, %v31, %v31, %v31
611 # CHECK: vaccf %v31, %v31, %v31
620 # CHECK: vaccg %v31, %v31, %v31
629 # CHECK: vacch %v31, %v31, %v31
[all …]
Dinsns-z14.txt476 # CHECK: vap %v0, %v0, %v31, 0, 0
479 # CHECK: vap %v0, %v31, %v0, 0, 0
482 # CHECK: vap %v31, %v0, %v0, 0, 0
494 # CHECK: vbperm %v0, %v0, %v31
500 # CHECK: vbperm %v0, %v31, %v0
506 # CHECK: vbperm %v31, %v0, %v0
521 # CHECK: vcp %v31, %v0, 0
527 # CHECK: vcp %v0, %v31, 0
545 # CHECK: vcvb %r0, %v31, 0
563 # CHECK: vcvbg %r0, %v31, 0
[all …]
/external/llvm/test/MC/AArch64/
Dneon-compare-instructions.s10 cmeq v1.16b, v31.16b, v8.16b
15 cmeq v3.2d, v31.2d, v21.2d
32 cmhs v1.16b, v31.16b, v8.16b
37 cmhs v3.2d, v31.2d, v21.2d
40 cmls v1.16b, v8.16b, v31.16b
45 cmls v3.2d, v21.2d, v31.2d
69 cmge v1.16b, v31.16b, v8.16b
74 cmge v3.2d, v31.2d, v21.2d
77 cmle v1.16b, v8.16b, v31.16b
82 cmle v3.2d, v21.2d, v31.2d
[all …]
Dneon-simd-ldst-multi-elem.s10 st1 { v31.4s }, [sp]
14 st1 { v31.2s }, [sp]
30 st1 { v31.4s, v0.4s }, [sp]
34 st1 { v31.2s, v0.2s }, [sp]
47 st1 { v31.4s-v0.4s }, [sp]
51 st1 { v31.2s-v0.2s }, [sp]
67 st1 { v31.4s, v0.4s, v1.4s }, [sp]
71 st1 { v31.2s, v0.2s, v1.2s }, [sp]
84 st1 { v31.4s-v1.4s }, [sp]
88 st1 { v31.2s-v1.2s }, [sp]
[all …]
Dneon-simd-ldst-one-elem.s10 ld1r { v31.4s }, [sp]
14 ld1r { v31.2s }, [sp]
31 ld2r { v31.4s, v0.4s }, [sp]
35 ld2r { v31.2s, v0.2s }, [sp]
36 ld2r { v31.1d, v0.1d }, [sp]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
[all …]
Dneon-simd-post-ldst-multi-elem.s10 ld1 { v31.4s }, [sp], #16
14 ld1 { v31.2s }, [sp], #8
39 ld1 { v31.4s, v0.4s }, [sp], #32
43 ld1 { v31.2s, v0.2s }, [sp], #16
68 ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
72 ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
97 ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
101 ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
126 ld2 { v31.4s, v0.4s }, [sp], #32
130 ld2 { v31.2s, v0.2s }, [sp], #16
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-compare-instructions.s10 cmeq v1.16b, v31.16b, v8.16b
15 cmeq v3.2d, v31.2d, v21.2d
32 cmhs v1.16b, v31.16b, v8.16b
37 cmhs v3.2d, v31.2d, v21.2d
40 cmls v1.16b, v8.16b, v31.16b
45 cmls v3.2d, v21.2d, v31.2d
69 cmge v1.16b, v31.16b, v8.16b
74 cmge v3.2d, v31.2d, v21.2d
77 cmle v1.16b, v8.16b, v31.16b
82 cmle v3.2d, v21.2d, v31.2d
[all …]
Dneon-simd-ldst-multi-elem.s10 st1 { v31.4s }, [sp]
14 st1 { v31.2s }, [sp]
30 st1 { v31.4s, v0.4s }, [sp]
34 st1 { v31.2s, v0.2s }, [sp]
47 st1 { v31.4s-v0.4s }, [sp]
51 st1 { v31.2s-v0.2s }, [sp]
67 st1 { v31.4s, v0.4s, v1.4s }, [sp]
71 st1 { v31.2s, v0.2s, v1.2s }, [sp]
84 st1 { v31.4s-v1.4s }, [sp]
88 st1 { v31.2s-v1.2s }, [sp]
[all …]
Dneon-simd-ldst-one-elem.s10 ld1r { v31.4s }, [sp]
14 ld1r { v31.2s }, [sp]
31 ld2r { v31.4s, v0.4s }, [sp]
35 ld2r { v31.2s, v0.2s }, [sp]
36 ld2r { v31.1d, v0.1d }, [sp]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
[all …]
Darmv8.6a-simd-matmul-error.s5 smmla v1.2s, v16.8b, v31.8b
7 summla v1.4s, v16.16b, v31.16b
17 usdot v31.2s, v1.8b, v2.4b[4]
19 usdot v31.4s, v1.16b, v2.4b[4]
21 sudot v31.2s, v1.8b, v2.4b[4]
23 sudot v31.4s, v1.16b, v2.4b[4]
27 usdot v31.4s, v1.8b, v2.4b[0]
29 usdot v31.2s, v1.16b, v2.4b[0]
31 sudot v31.4s, v1.8b, v2.4b[0]
33 sudot v31.2s, v1.16b, v2.4b[0]
Dneon-simd-post-ldst-multi-elem.s10 ld1 { v31.4s }, [sp], #16
14 ld1 { v31.2s }, [sp], #8
39 ld1 { v31.4s, v0.4s }, [sp], #32
43 ld1 { v31.2s, v0.2s }, [sp], #16
68 ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
72 ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
97 ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
101 ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
126 ld2 { v31.4s, v0.4s }, [sp], #32
130 ld2 { v31.2s, v0.2s }, [sp], #16
[all …]
Dneon-mov.s13 movi v31.2s, #1, lsl #24
48 mvni v31.4s, #1, lsl #24
83 bic v31.8h, #1, lsl #8
111 orr v31.4h, #1
136 movi v31.4s, #1, msl #16
148 mvni v31.4s, #0x1, msl #8
160 movi v31.8b, #0xff
162 movi v31.16b, #0x1f
188 fmov v31.2d, #1.0
199 mov v0.8b, v31.8b
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-compare-instructions.s.cs3 0xe1,0x8f,0x28,0x6e = cmeq v1.16b, v31.16b, v8.16b
8 0xe3,0x8f,0xf5,0x6e = cmeq v3.2d, v31.2d, v21.2d
10 0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b
15 0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d
17 0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b
22 0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d
24 0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b
29 0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d
31 0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b
36 0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d
[all …]
Dneon-simd-ldst-one-elem.s.cs4 0xff,0xcb,0x40,0x4d = ld1r {v31.4s}, [sp]
8 0xff,0xcb,0x40,0x0d = ld1r {v31.2s}, [sp]
12 0xff,0xcb,0x60,0x4d = ld2r {v31.4s, v0.4s}, [sp]
16 0xff,0xcb,0x60,0x0d = ld2r {v31.2s, v0.2s}, [sp]
17 0xff,0xcf,0x60,0x0d = ld2r {v31.1d, v0.1d}, [sp]
20 0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp]
24 0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp]
25 0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp]
28 0xff,0xeb,0x60,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
32 0xff,0xeb,0x60,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
[all …]
Dneon-simd-ldst-multi-elem.s.cs4 0xff,0x7b,0x00,0x4c = st1 {v31.4s}, [sp]
8 0xff,0x7b,0x00,0x0c = st1 {v31.2s}, [sp]
12 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp]
16 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp]
20 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp]
24 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp]
28 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp]
32 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp]
36 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp]
40 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp]
[all …]
Dneon-simd-post-ldst-multi-elem.s.cs4 0xff,0x7b,0xdf,0x4c = ld1 {v31.4s}, [sp], #16
8 0xff,0x7b,0xdf,0x0c = ld1 {v31.2s}, [sp], #8
12 0xff,0xab,0xdf,0x4c = ld1 {v31.4s, v0.4s}, [sp], #32
16 0xff,0xab,0xdf,0x0c = ld1 {v31.2s, v0.2s}, [sp], #16
20 0xff,0x6b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48
24 0xff,0x6b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24
28 0xff,0x2b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
32 0xff,0x2b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
36 0xff,0x8b,0xdf,0x4c = ld2 {v31.4s, v0.4s}, [sp], #32
40 0xff,0x8b,0xdf,0x0c = ld2 {v31.2s, v0.2s}, [sp], #16
[all …]
/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s107 ext v31.8b, v2.8b , v3.8b , #5
110 uaddl v8.8h, v31.8b, v2.8b //// a0 + a5 (column1,row0)
120 ext v31.8b, v2.8b , v3.8b , #2
123 umlal v8.8h, v31.8b, v1.8b //// a0 + a5 + 20a2 (column1,row0)
133 ext v31.8b, v2.8b , v3.8b , #3
136 umlal v8.8h, v31.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column1,row0)
146 ext v31.8b, v2.8b , v3.8b , #1
149 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row0)
159 ext v31.8b, v2.8b , v3.8b , #4
162 umlsl v8.8h, v31.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row0)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpartial-sgpr-to-vgpr-spills.ll688 ; GCN-NEXT: v_writelane_b32 v31, s4, 0
689 ; GCN-NEXT: v_writelane_b32 v31, s5, 1
690 ; GCN-NEXT: v_writelane_b32 v31, s6, 2
691 ; GCN-NEXT: v_writelane_b32 v31, s7, 3
692 ; GCN-NEXT: v_writelane_b32 v31, s8, 4
693 ; GCN-NEXT: v_writelane_b32 v31, s9, 5
694 ; GCN-NEXT: v_writelane_b32 v31, s10, 6
695 ; GCN-NEXT: v_writelane_b32 v31, s11, 7
696 ; GCN-NEXT: v_writelane_b32 v31, s12, 8
697 ; GCN-NEXT: v_writelane_b32 v31, s13, 9
[all …]
/external/libhevc/common/arm64/
Dihevc_inter_pred_luma_vert_w16inp_w16out.s214 smull v31.4s,v4.4h,v23.4h
215 smlal v31.4s,v3.4h,v22.4h
216 smlal v31.4s,v5.4h,v24.4h
217 smlal v31.4s,v6.4h,v25.4h
219 smlal v31.4s,v7.4h,v26.4h
221 smlal v31.4s,v16.4h,v27.4h
223 smlal v31.4s,v17.4h,v28.4h
225 smlal v31.4s,v18.4h,v29.4h
256 sub v31.4S, v31.4s, v30.4s
275 shrn v31.4h, v31.4s, #6
[all …]
/external/libavc/common/armv8/
Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s140 movi v31.8b, #5 // Filter coeff 5
160 umlsl v24.8h, v2.8b, v31.8b
161 umlsl v24.8h, v8.8b, v31.8b
171 umlsl v28.8h, v19.8b, v31.8b
172 umlsl v28.8h, v22.8b, v31.8b
177 umlsl v24.8h, v3.8b, v31.8b
178 umlsl v24.8h, v9.8b, v31.8b
192 umlsl v24.8h, v19.8b, v31.8b
193 umlsl v24.8h, v22.8b, v31.8b
198 umlsl v16.8h, v4.8b, v31.8b
[all …]

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