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Searched refs:v32f16 (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h124 v32f16 = 69, // 32 x f16 enumerator
367 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v16f32 || in is512BitVector()
513 case v32f16: in getVectorElementType()
578 case v32f16: in getVectorNumElements()
795 case v32f16: in getSizeInBits()
990 if (NumElements == 32) return MVT::v32f16; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h128 v32f16 = 73, // 32 x f16 enumerator
399 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v32bf16 || in is512BitVector()
585 case v32f16: in getVectorElementType()
683 case v32f16: in getVectorNumElements()
931 case v32f16: in getSizeInBits()
1180 if (NumElements == 32) return MVT::v32f16; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-fp-rounding.ll77 %res = call <32 x half> @llvm.ceil.v32f16(<32 x half> %op)
324 %res = call <32 x half> @llvm.floor.v32f16(<32 x half> %op)
571 %res = call <32 x half> @llvm.nearbyint.v32f16(<32 x half> %op)
818 %res = call <32 x half> @llvm.rint.v32f16(<32 x half> %op)
1065 %res = call <32 x half> @llvm.round.v32f16(<32 x half> %op)
1312 %res = call <32 x half> @llvm.trunc.v32f16(<32 x half> %op)
1510 declare <32 x half> @llvm.ceil.v32f16(<32 x half>)
1529 declare <32 x half> @llvm.floor.v32f16(<32 x half>)
1548 declare <32 x half> @llvm.nearbyint.v32f16(<32 x half>)
1567 declare <32 x half> @llvm.rint.v32f16(<32 x half>)
[all …]
Dsve-fixed-length-fp-reduce.ll74 %res = call half @llvm.vector.reduce.fadd.v32f16(half %start, <32 x half> %op)
302 %res = call fast half @llvm.vector.reduce.fadd.v32f16(half %start, <32 x half> %op)
535 %res = call half @llvm.vector.reduce.fmax.v32f16(<32 x half> %op)
752 %res = call half @llvm.vector.reduce.fmin.v32f16(<32 x half> %op)
925 declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
946 declare half @llvm.vector.reduce.fmax.v32f16(<32 x half>)
967 declare half @llvm.vector.reduce.fmin.v32f16(<32 x half>)
Dsve-fixed-length-fp-minmax.ll84 %res = call <32 x half> @llvm.maxnum.v32f16(<32 x half> %op1, <32 x half> %op2)
364 %res = call <32 x half> @llvm.minnum.v32f16(<32 x half> %op1, <32 x half> %op2)
588 declare <32 x half> @llvm.minnum.v32f16(<32 x half>, <32 x half>)
607 declare <32 x half> @llvm.maxnum.v32f16(<32 x half>, <32 x half>)
Dsve-fixed-length-fp-arith.ll598 %res = call <32 x half> @llvm.fma.v32f16(<32 x half> %op1, <32 x half> %op2, <32 x half> %op3)
1304 %res = call <32 x half> @llvm.sqrt.v32f16(<32 x half> %op)
1718 declare <32 x half> @llvm.fma.v32f16(<32 x half>, <32 x half>, <32 x half>)
1737 declare <32 x half> @llvm.sqrt.v32f16(<32 x half>)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp214 case MVT::v32f16: return VectorType::get(Type::getHalfTy(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td96 def v32f16 : ValueType<512, 69>; // 8 x f16 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td101 def v32f16 : ValueType<512, 73>; // 32 x f16 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp314 case MVT::v32f16: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp139 case MVT::v32f16: return "MVT::v32f16"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp158 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
222 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp180 setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()
264 setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); in AMDGPUTargetLowering()