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Searched refs:v3i16 (Results 1 – 25 of 34) sorted by relevance

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/external/clang/test/CodeGen/
Dppc64-vector.c4 typedef short v3i16 __attribute__((vector_size (6))); typedef
19 v3i16 test_v3i16(v3i16 x) in test_v3i16()
/external/llvm-project/clang/test/CodeGen/
Dppc64-vector.c4 typedef short v3i16 __attribute__((vector_size (6))); typedef
19 v3i16 test_v3i16(v3i16 x) in test_v3i16()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h84 v3i16 = 36, // 3 x i16 enumerator
462 case v3i16: in getVectorElementType()
632 case v3i16: in getVectorNumElements()
732 case v3i16: in getSizeInBits()
949 if (NumElements == 3) return MVT::v3i16; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h85 v3i16 = 37, // 3 x i16 enumerator
531 case v3i16: in getVectorElementType()
747 case v3i16: in getVectorNumElements()
860 case v3i16: in getSizeInBits()
1136 if (NumElements == 3) return MVT::v3i16; in getVectorVT()
/external/llvm/test/CodeGen/X86/
Dwiden_arith-3.ll4 ; Widen a v3i16 to v8i16 to do a vector add
/external/llvm-project/llvm/test/CodeGen/X86/
Dwiden_arith-3.ll4 ; Widen a v3i16 to v8i16 to do a vector add
Dvec_setcc.ll201 ; This asserted in type legalization for v3i1 setcc after v3i16 was made
/external/llvm-project/llvm/test/Transforms/EarlyCSE/
Dcommute.ll1036 ; CHECK-NEXT: [[X:%.*]] = call <3 x i16> @llvm.smul.fix.sat.v3i16(<3 x i16> [[A:%.*]], <3 x i16>…
1037 ; CHECK-NEXT: [[Y:%.*]] = call <3 x i16> @llvm.smul.fix.sat.v3i16(<3 x i16> [[B]], <3 x i16> [[A…
1041 %x = call <3 x i16> @llvm.smul.fix.sat.v3i16(<3 x i16> %a, <3 x i16> %b, i32 2)
1042 %y = call <3 x i16> @llvm.smul.fix.sat.v3i16(<3 x i16> %b, <3 x i16> %a, i32 2)
1051 ; CHECK-NEXT: [[X:%.*]] = call <3 x i16> @llvm.umul.fix.sat.v3i16(<3 x i16> [[A:%.*]], <3 x i16>…
1052 ; CHECK-NEXT: [[Y:%.*]] = call <3 x i16> @llvm.umul.fix.sat.v3i16(<3 x i16> [[B]], <3 x i16> [[A…
1056 %x = call <3 x i16> @llvm.umul.fix.sat.v3i16(<3 x i16> %a, <3 x i16> %b, i32 3)
1057 %y = call <3 x i16> @llvm.umul.fix.sat.v3i16(<3 x i16> %b, <3 x i16> %a, i32 3)
1151 declare <3 x i16> @llvm.smul.fix.sat.v3i16(<3 x i16>, <3 x i16>, i32)
1152 declare <3 x i16> @llvm.umul.fix.sat.v3i16(<3 x i16>, <3 x i16>, i32)
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsaddsat.ll231 %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
435 declare <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16>, <3 x i16>) #0
Dusubsat.ll162 %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
482 declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0
Dbswap.ll7 declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>) nounwind readnone
510 %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src)
Duaddsat.ll161 %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
512 declare <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16>, <3 x i16>) #0
Dfshr.ll13 declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>)
691 %ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2)
Dssubsat.ll232 %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
994 declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dfsh.ll597 declare <3 x i16> @llvm.fshl.v3i16(<3 x i16>, <3 x i16>, <3 x i16>)
621 ; CHECK-NEXT: [[R:%.*]] = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> [[X:%.*]])
624 %r = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %x, <3 x i16> %x, <3 x i16> <i16 8, i16 8, i16 8>)
Drotate.ll368 ; CHECK-NEXT: [[R:%.*]] = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> [[X:%.*]], <3 x i16> [[X]], …
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dbswap.ll501 ; %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %ext.src)
544 declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>) #1
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp181 case MVT::v3i16: return VectorType::get(Type::getInt16Ty(Context), 3); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td59 def v3i16 : ValueType<48 , 36>; // 3 x i16 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td61 def v3i16 : ValueType<48 , 37>; // 3 x i16 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp242 case MVT::v3i16: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp103 case MVT::v3i16: return "MVT::v3i16"; in getEnumName()
/external/deqp/external/vulkancts/modules/vulkan/ray_tracing/
DvktRayTracingDataSpillTests.cpp1397 using v3i16 = tcu::Vector<deInt16, 3>; typedef
1528 else if (dataType == DataType::INT16) GEN_V3_FILL(v3i16); in fillInputBuffer()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DBUFInstructions.td1234 …efm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v4i16, "BUFFER_LOAD_FORMAT_D16_XYZ", v3i16>;
1323 … : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v4i16, "BUFFER_STORE_FORMAT_D16_XYZ", v3i16>;

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