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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
200 { ISD::SHL, MVT::v4i64, 2 }, in getArithmeticInstrCost()
201 { ISD::SRL, MVT::v4i64, 4 }, in getArithmeticInstrCost()
202 { ISD::SRA, MVT::v4i64, 4 }, in getArithmeticInstrCost()
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
253 { ISD::SHL, MVT::v4i64, 2 }, // psllq. in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp305 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
488 { ISD::MUL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
533 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
567 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
568 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
610 { ISD::SHL, MVT::v4i64, 2+2 }, in getArithmeticInstrCost()
611 { ISD::SRL, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
612 { ISD::SRA, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/Verifier/
Dintrinsic-arg-overloading-struct-ret.ll14 ; CHECK-NEXT: llvm.aarch64.neon.ld2lane.v4i64
16 …%res = call { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i64(<4 x i64> %a, <4 x i64> %b, …
19 declare { <4 x i64>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i64(<4 x i64>, <4 x i64>, i64, i8*)
40 ; CHECK-NEXT: llvm.aarch64.neon.ld3lane.v4i64
42 …%res = call { <4 x i64>, <4 x i32>, <4 x i64> } @llvm.aarch64.neon.ld3lane.v4i64(<4 x i64> %a, <4 …
45 declare { <4 x i64>, <4 x i32>, <4 x i64> } @llvm.aarch64.neon.ld3lane.v4i64(<4 x i64>, <4 x i64>, …
66 ; CHECK-NEXT: llvm.aarch64.neon.ld4lane.v4i64
68 …%res = call { <4 x i64>, <4 x i64>, <4 x i32>, <4 x i64> } @llvm.aarch64.neon.ld4lane.v4i64(<4 x i…
71 declare { <4 x i64>, <4 x i64>, <4 x i32>, <4 x i64> } @llvm.aarch64.neon.ld4lane.v4i64(<4 x i64>, …
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp318 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
343 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
553 { ISD::MUL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
586 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
621 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
622 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
677 { ISD::SHL, MVT::v4i64, 2+2 }, in getArithmeticInstrCost()
678 { ISD::SRL, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
679 { ISD::SRA, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
700 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/Transforms/GVN/
Dmasked-load-store-vn-crash.ll8 ; CHECK-NEXT: [[WIDE_MASKED_LOAD_1_I:%.*]] = tail call <4 x i64> @llvm.masked.load.v4i64.p0v4i64…
12 …%wide.masked.load.1.i = tail call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* nonnull bit…
15 …%wide.masked.load614.1.i = tail call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* nonnull …
20 declare <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>*, i32 immarg, <4 x i1>, <4 x i64>)
/external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/
Dmasked-store-load.ll14 declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
19 …tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
32 ; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %[[A]], <4 x i64>* %[[D]], i32 1, <4 …
48 ; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i…
64 ; ADDR: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1…
83 ; CHECK: %[[E:.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %[[D]], i32 1, <4 x …
109 …tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
117 ; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* %[[D]], i…
118 ; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i…
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h97 v4i64 = 47, // 4 x i64 enumerator
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
351 case v4i64: in getVectorElementType()
407 case v4i64: in getVectorNumElements()
493 case v4i64: in getSizeInBits()
635 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dbswap.ll15 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
38 …nd an estimated cost of 14 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
42 …und an estimated cost of 2 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
46 …und an estimated cost of 4 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
50 …und an estimated cost of 1 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
53 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
Darith-uminmax.ll13 declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)
35 … estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
54 … estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
73 …n estimated cost of 4 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
92 …n estimated cost of 5 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
111 …n estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
130 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
149 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
168 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <…
186 %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <4 x i64> undef)
[all …]
Darith-sminmax.ll13 declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)
35 … estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
54 … estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
73 …n estimated cost of 4 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
92 …n estimated cost of 5 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
111 …n estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
130 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
149 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
168 …n estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <…
186 %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <4 x i64> undef)
[all …]
Darith-usat.ll20 declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
42 …imated cost of 24 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
61 …timated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
80 …timated cost of 9 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
99 …timated cost of 3 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
118 …timated cost of 3 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
137 …timated cost of 3 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
156 …timated cost of 3 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
175 …imated cost of 14 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
194 …timated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <…
[all …]
/external/llvm-project/llvm/test/CodeGen/SPARC/
Dfshl.ll36 …%i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, …
48 declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll11 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
39 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dfold-vector-sext-crash.ll6 ; due to an illegal build_vector of type MVT::v4i64.
/external/llvm-project/llvm/test/CodeGen/Generic/
Dbswap.ll20 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>);
45 %r2 = tail call <4 x i64> @llvm.bswap.v4i64(<4 x i64> <i64 272, i64 272, i64 272, i64 272>)
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h109 v4i64 = 59, // 4 x i64 enumerator
362 SimpleTy == MVT::v4i64 || SimpleTy == MVT::v256i1); in is256BitVector()
497 case v4i64: in getVectorElementType()
620 case v4i64: in getVectorNumElements()
780 case v4i64: in getSizeInBits()
976 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-add.ll11 …estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
19 …estimated cost of 29 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
27 …estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
35 …estimated cost of 29 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
42 %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
101 declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
/external/llvm-project/llvm/test/Instrumentation/HeapProfiler/
Dmasked-load-store.ll15 @v4i64 = global <4 x i32*>* zeroinitializer, align 8
61 define void @store.v4i64.0001(<4 x i32*> %arg) {
62 ; ALL-LABEL: @store.v4i64.0001
63 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
175 define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) {
176 ; ALL-LABEL: @load.v4i64.0001
177 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1322 …dd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPADDQYrr:{ *:[v4i64]…
1333 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPADDQZ256rr:{ *:[v4i6…
1910 …ub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPSUBQYrr:{ *:[v4i64]…
1921 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPSUBQZ256rr:{ *:[v4i6…
2390 … *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMULLQZ256rr:{ *:[v4i6…
3622 …and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPANDYrr:{ *:[v4i64]…
3633 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPANDQZ256rr:{ *:[v4i6…
3644 …nd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VANDPSYrr:{ *:[v4i64]…
5196 …(or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPORYrr:{ *:[v4i64] …
5207 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPORQZ256rr:{ *:[v4i64…
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dfold-vector-sext-crash.ll7 ; due to an illegal build_vector of type MVT::v4i64.
/external/llvm/test/CodeGen/AArch64/
Daarch64-vcvtfp2fxs-combine.ll6 ; with a v4f64 input. Since v4i64 is not legal we should bail out. We can
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-vcvtfp2fxs-combine.ll6 ; with a v4f64 input. Since v4i64 is not legal we should bail out. We can
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll15 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
34 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)
99 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)
127 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 0)
136 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 1)
255 declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)
283 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 0)
292 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 1)

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