| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 51 const LLT v4s32 = LLT::vector(4, 32); in AArch64LegalizerInfo() local
62 .legalFor({p0, s1, s8, s16, s32, s64, v2s32, v4s32, v2s64}) in AArch64LegalizerInfo()
79 .legalFor({p0, s16, s32, s64, v2s32, v4s32, v2s64}) in AArch64LegalizerInfo()
84 .legalFor({s32, s64, v4s32, v2s32, v2s64}) in AArch64LegalizerInfo()
89 .legalFor({s32, s64, v2s32, v4s32, v2s64, v8s16, v16s8}) in AArch64LegalizerInfo()
92 .clampNumElements(0, v2s32, v4s32) in AArch64LegalizerInfo()
98 {v2s32, v2s32}, {v4s32, v4s32}, {v2s64, v2s64}}) in AArch64LegalizerInfo()
102 .clampNumElements(0, v2s32, v4s32) in AArch64LegalizerInfo()
131 {v4s32, v4s32}, in AArch64LegalizerInfo()
150 .legalFor({s32, s64, v2s64, v4s32, v2s32}); in AArch64LegalizerInfo()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64LegalizerInfo.cpp | 55 const LLT v4s32 = LLT::vector(4, 32); in AArch64LegalizerInfo() local
60 v16s8, v8s16, v4s32, in AArch64LegalizerInfo()
103 .legalFor({s32, s64, v4s32, v2s32, v2s64}) in AArch64LegalizerInfo()
108 .legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8}) in AArch64LegalizerInfo()
117 .clampNumElements(0, v2s32, v4s32) in AArch64LegalizerInfo()
137 {v4s32, v4s32}, in AArch64LegalizerInfo()
143 .clampNumElements(0, v2s32, v4s32) in AArch64LegalizerInfo()
173 .legalFor({s32, s64, v2s64, v4s32, v2s32}) in AArch64LegalizerInfo()
174 .clampNumElements(0, v2s32, v4s32) in AArch64LegalizerInfo()
198 .legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16}); in AArch64LegalizerInfo()
[all …]
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86LegalizerInfo.cpp | 285 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE1() local
289 for (auto Ty : {s32, v4s32}) in setLegalizerInfoSSE1()
293 for (auto Ty : {v4s32, v2s64}) in setLegalizerInfoSSE1()
300 for (const auto &Ty : {v4s32, v2s64}) { in setLegalizerInfoSSE1()
316 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE2() local
329 for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) in setLegalizerInfoSSE2()
345 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) { in setLegalizerInfoSSE2()
349 for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) { in setLegalizerInfoSSE2()
359 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE41() local
361 setAction({G_MUL, v4s32}, Legal); in setLegalizerInfoSSE41()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86LegalizerInfo.cpp | 290 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE1() local
294 for (auto Ty : {s32, v4s32}) in setLegalizerInfoSSE1()
298 for (auto Ty : {v4s32, v2s64}) in setLegalizerInfoSSE1()
305 for (const auto &Ty : {v4s32, v2s64}) { in setLegalizerInfoSSE1()
321 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE2() local
334 for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) in setLegalizerInfoSSE2()
350 {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) { in setLegalizerInfoSSE2()
354 for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) { in setLegalizerInfoSSE2()
364 const LLT v4s32 = LLT::vector(4, 32); in setLegalizerInfoSSE41() local
366 setAction({G_MUL, v4s32}, Legal); in setLegalizerInfoSSE41()
[all …]
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 1032 "llvm.nvvm.tex.1d.v4s32.s32">;
1036 "llvm.nvvm.tex.1d.v4s32.f32">;
1040 "llvm.nvvm.tex.1d.level.v4s32.f32">;
1045 "llvm.nvvm.tex.1d.grad.v4s32.f32">;
1085 "llvm.nvvm.tex.1d.array.v4s32.s32">;
1089 "llvm.nvvm.tex.1d.array.v4s32.f32">;
1094 "llvm.nvvm.tex.1d.array.level.v4s32.f32">;
1099 "llvm.nvvm.tex.1d.array.grad.v4s32.f32">;
1140 "llvm.nvvm.tex.2d.v4s32.s32">;
1144 "llvm.nvvm.tex.2d.v4s32.f32">;
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 61 const LLT v4s32 = LLT::vector(4, 32); in MipsLegalizerInfo() local
69 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
93 {v4s32, p0, 128, false}, in MipsLegalizerInfo()
149 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
213 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 1330 "llvm.nvvm.tex.1d.v4s32.s32">;
1334 "llvm.nvvm.tex.1d.v4s32.f32">;
1338 "llvm.nvvm.tex.1d.level.v4s32.f32">;
1343 "llvm.nvvm.tex.1d.grad.v4s32.f32">;
1383 "llvm.nvvm.tex.1d.array.v4s32.s32">;
1387 "llvm.nvvm.tex.1d.array.v4s32.f32">;
1392 "llvm.nvvm.tex.1d.array.level.v4s32.f32">;
1397 "llvm.nvvm.tex.1d.array.grad.v4s32.f32">;
1438 "llvm.nvvm.tex.2d.v4s32.s32">;
1442 "llvm.nvvm.tex.2d.v4s32.f32">;
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 1337 "llvm.nvvm.tex.1d.v4s32.s32">;
1341 "llvm.nvvm.tex.1d.v4s32.f32">;
1345 "llvm.nvvm.tex.1d.level.v4s32.f32">;
1350 "llvm.nvvm.tex.1d.grad.v4s32.f32">;
1390 "llvm.nvvm.tex.1d.array.v4s32.s32">;
1394 "llvm.nvvm.tex.1d.array.v4s32.f32">;
1399 "llvm.nvvm.tex.1d.array.level.v4s32.f32">;
1404 "llvm.nvvm.tex.1d.array.grad.v4s32.f32">;
1445 "llvm.nvvm.tex.2d.v4s32.s32">;
1449 "llvm.nvvm.tex.2d.v4s32.f32">;
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | legalize-insert-vector-elt.mir | 43 name: v4s32
47 ; CHECK-LABEL: name: v4s32
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 77 const LLT v4s32 = LLT::vector(4, 32); in MipsLegalizerInfo() local
85 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
117 {v4s32, p0, 128, NoAlignRequirements}, in MipsLegalizerInfo()
200 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
283 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
|
| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | LegalizerInfoTest.cpp | 222 const LLT v4s32 = LLT::vector(4, 32); in TEST() local
234 .legalFor({v4s32, v4p0}) in TEST()
241 EXPECT_ACTION(MoreElements, 0, v4s32, LegalityQuery(G_IMPLICIT_DEF, {v3s32})); in TEST()
|
| /external/llvm-project/llvm/docs/GlobalISel/ |
| D | Legalizer.rst | 63 .legalFor({s32, s64, v2s32, v4s32, v2s64})
66 .clampNumElements(0, v2s32, v4s32)
125 .legalFor({s32, s64, v2s32, v4s32, v2s64})
|
| /external/deqp/external/vulkancts/modules/vulkan/robustness/ |
| D | vktRobustBufferAccessWithVariablePointersTests.cpp | 745 , v4s32(autoincrement) in Variables()
788 const Variable v4s32; member in vkt::robustness::__anonebaadb960111::Variables
987 (var.v4s32, is, op::TypeVector, var.s32, 4) in MakeShader()
1004 shaderSource.makeSame(var.buffer_type_vec, var.v4s32); in MakeShader()
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 3601 nvvm_tex_1d_array_grad_v4s32_f32, // llvm.nvvm.tex.1d.array.grad.v4s32.f32
3604 nvvm_tex_1d_array_level_v4s32_f32, // llvm.nvvm.tex.1d.array.level.v4s32.f32
3608 nvvm_tex_1d_array_v4s32_f32, // llvm.nvvm.tex.1d.array.v4s32.f32
3609 nvvm_tex_1d_array_v4s32_s32, // llvm.nvvm.tex.1d.array.v4s32.s32
3613 nvvm_tex_1d_grad_v4s32_f32, // llvm.nvvm.tex.1d.grad.v4s32.f32
3616 nvvm_tex_1d_level_v4s32_f32, // llvm.nvvm.tex.1d.level.v4s32.f32
3620 nvvm_tex_1d_v4s32_f32, // llvm.nvvm.tex.1d.v4s32.f32
3621 nvvm_tex_1d_v4s32_s32, // llvm.nvvm.tex.1d.v4s32.s32
3625 nvvm_tex_2d_array_grad_v4s32_f32, // llvm.nvvm.tex.2d.array.grad.v4s32.f32
3628 nvvm_tex_2d_array_level_v4s32_f32, // llvm.nvvm.tex.2d.array.level.v4s32.f32
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 3601 nvvm_tex_1d_array_grad_v4s32_f32, // llvm.nvvm.tex.1d.array.grad.v4s32.f32
3604 nvvm_tex_1d_array_level_v4s32_f32, // llvm.nvvm.tex.1d.array.level.v4s32.f32
3608 nvvm_tex_1d_array_v4s32_f32, // llvm.nvvm.tex.1d.array.v4s32.f32
3609 nvvm_tex_1d_array_v4s32_s32, // llvm.nvvm.tex.1d.array.v4s32.s32
3613 nvvm_tex_1d_grad_v4s32_f32, // llvm.nvvm.tex.1d.grad.v4s32.f32
3616 nvvm_tex_1d_level_v4s32_f32, // llvm.nvvm.tex.1d.level.v4s32.f32
3620 nvvm_tex_1d_v4s32_f32, // llvm.nvvm.tex.1d.v4s32.f32
3621 nvvm_tex_1d_v4s32_s32, // llvm.nvvm.tex.1d.v4s32.s32
3625 nvvm_tex_2d_array_grad_v4s32_f32, // llvm.nvvm.tex.2d.array.grad.v4s32.f32
3628 nvvm_tex_2d_array_level_v4s32_f32, // llvm.nvvm.tex.2d.array.level.v4s32.f32
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 3601 nvvm_tex_1d_array_grad_v4s32_f32, // llvm.nvvm.tex.1d.array.grad.v4s32.f32
3604 nvvm_tex_1d_array_level_v4s32_f32, // llvm.nvvm.tex.1d.array.level.v4s32.f32
3608 nvvm_tex_1d_array_v4s32_f32, // llvm.nvvm.tex.1d.array.v4s32.f32
3609 nvvm_tex_1d_array_v4s32_s32, // llvm.nvvm.tex.1d.array.v4s32.s32
3613 nvvm_tex_1d_grad_v4s32_f32, // llvm.nvvm.tex.1d.grad.v4s32.f32
3616 nvvm_tex_1d_level_v4s32_f32, // llvm.nvvm.tex.1d.level.v4s32.f32
3620 nvvm_tex_1d_v4s32_f32, // llvm.nvvm.tex.1d.v4s32.f32
3621 nvvm_tex_1d_v4s32_s32, // llvm.nvvm.tex.1d.v4s32.s32
3625 nvvm_tex_2d_array_grad_v4s32_f32, // llvm.nvvm.tex.2d.array.grad.v4s32.f32
3628 nvvm_tex_2d_array_level_v4s32_f32, // llvm.nvvm.tex.2d.array.level.v4s32.f32
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Intrinsics.gen | 3601 nvvm_tex_1d_array_grad_v4s32_f32, // llvm.nvvm.tex.1d.array.grad.v4s32.f32
3604 nvvm_tex_1d_array_level_v4s32_f32, // llvm.nvvm.tex.1d.array.level.v4s32.f32
3608 nvvm_tex_1d_array_v4s32_f32, // llvm.nvvm.tex.1d.array.v4s32.f32
3609 nvvm_tex_1d_array_v4s32_s32, // llvm.nvvm.tex.1d.array.v4s32.s32
3613 nvvm_tex_1d_grad_v4s32_f32, // llvm.nvvm.tex.1d.grad.v4s32.f32
3616 nvvm_tex_1d_level_v4s32_f32, // llvm.nvvm.tex.1d.level.v4s32.f32
3620 nvvm_tex_1d_v4s32_f32, // llvm.nvvm.tex.1d.v4s32.f32
3621 nvvm_tex_1d_v4s32_s32, // llvm.nvvm.tex.1d.v4s32.s32
3625 nvvm_tex_2d_array_grad_v4s32_f32, // llvm.nvvm.tex.2d.array.grad.v4s32.f32
3628 nvvm_tex_2d_array_level_v4s32_f32, // llvm.nvvm.tex.2d.array.level.v4s32.f32
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 3595 nvvm_tex_1d_array_grad_v4s32_f32, // llvm.nvvm.tex.1d.array.grad.v4s32.f32
3598 nvvm_tex_1d_array_level_v4s32_f32, // llvm.nvvm.tex.1d.array.level.v4s32.f32
3602 nvvm_tex_1d_array_v4s32_f32, // llvm.nvvm.tex.1d.array.v4s32.f32
3603 nvvm_tex_1d_array_v4s32_s32, // llvm.nvvm.tex.1d.array.v4s32.s32
3607 nvvm_tex_1d_grad_v4s32_f32, // llvm.nvvm.tex.1d.grad.v4s32.f32
3610 nvvm_tex_1d_level_v4s32_f32, // llvm.nvvm.tex.1d.level.v4s32.f32
3614 nvvm_tex_1d_v4s32_f32, // llvm.nvvm.tex.1d.v4s32.f32
3615 nvvm_tex_1d_v4s32_s32, // llvm.nvvm.tex.1d.v4s32.s32
3619 nvvm_tex_2d_array_grad_v4s32_f32, // llvm.nvvm.tex.2d.array.grad.v4s32.f32
3622 nvvm_tex_2d_array_level_v4s32_f32, // llvm.nvvm.tex.2d.array.level.v4s32.f32
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 5110 "llvm.nvvm.tex.1d.array.grad.v4s32.f32",
5113 "llvm.nvvm.tex.1d.array.level.v4s32.f32",
5117 "llvm.nvvm.tex.1d.array.v4s32.f32",
5118 "llvm.nvvm.tex.1d.array.v4s32.s32",
5122 "llvm.nvvm.tex.1d.grad.v4s32.f32",
5125 "llvm.nvvm.tex.1d.level.v4s32.f32",
5129 "llvm.nvvm.tex.1d.v4s32.f32",
5130 "llvm.nvvm.tex.1d.v4s32.s32",
5134 "llvm.nvvm.tex.2d.array.grad.v4s32.f32",
5137 "llvm.nvvm.tex.2d.array.level.v4s32.f32",
[all …]
|