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Searched refs:v4u32 (Results 1 – 25 of 33) sorted by relevance

12

/external/webp/src/dsp/
Drescaler_msa.c28 v4u32 tmp0, tmp1, tmp2, tmp3; \
48 v4u32 tmp0, tmp1; \
62 v4u32 tmp0, tmp1, tmp2, tmp3; \
79 v4u32 tmp0, tmp1; \
84 dst = (v4u32)__msa_pckev_w((v4i32)out1, (v4i32)out0); \
89 v4u32 tmp0, tmp1, tmp2, tmp3; \
103 v4u32 tmp0, tmp1; \
120 const v4u32 scale = (v4u32)__msa_fill_w(wrk->fy_scale); in ExportRowExpand_0()
121 const v4u32 shift = (v4u32)__msa_fill_w(WEBP_RESCALER_RFIX); in ExportRowExpand_0()
125 v4u32 src0, src1, src2, src3; in ExportRowExpand_0()
[all …]
Dmsa_macro.h57 #define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
69 #define ST_UW(...) ST_W(v4u32, __VA_ARGS__)
274 #define LD_UW2(...) LD_W2(v4u32, __VA_ARGS__)
281 #define LD_UW3(...) LD_W3(v4u32, __VA_ARGS__)
288 #define LD_UW4(...) LD_W4(v4u32, __VA_ARGS__)
328 #define ST_UW2(...) ST_W2(v4u32, __VA_ARGS__)
335 #define ST_UW3(...) ST_W3(v4u32, __VA_ARGS__)
342 #define ST_UW4(...) ST_W4(v4u32, __VA_ARGS__)
504 out0 = (RTYPE)__msa_dotp_u_d((v4u32)mult0, (v4u32)cnst0); \
505 out1 = (RTYPE)__msa_dotp_u_d((v4u32)mult1, (v4u32)cnst1); \
[all …]
Dupsampling_msa.c26 out0 = (v4u32)__msa_ilvr_h((v8i16)zero, t0); \
27 out1 = (v4u32)__msa_ilvl_h((v8i16)zero, t0); \
39 v4u32 temp0, temp1, temp2, temp3; \
47 v4u32 temp0, temp1; \
118 v4u32 p0, p1, p2, p3; \
138 v4u32 p0, p1; \
/external/libaom/libaom/aom_dsp/mips/
Dintrapred_msa.c161 v4u32 sum_w; in intra_predict_dc_4x4_msa()
170 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_4x4_msa()
182 v4u32 sum_w; in intra_predict_dc_tl_4x4_msa()
188 sum_w = (v4u32)__msa_srari_w((v4i32)sum_w, 2); in intra_predict_dc_tl_4x4_msa()
211 v4u32 sum_w; in intra_predict_dc_8x8_msa()
220 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d); in intra_predict_dc_8x8_msa()
222 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 4); in intra_predict_dc_8x8_msa()
237 v4u32 sum_w; in intra_predict_dc_tl_8x8_msa()
245 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_tl_8x8_msa()
270 v4u32 sum_w; in intra_predict_dc_16x16_msa()
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dintrapred_msa.c159 v4u32 sum_w; in intra_predict_dc_4x4_msa()
168 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_4x4_msa()
180 v4u32 sum_w; in intra_predict_dc_tl_4x4_msa()
186 sum_w = (v4u32)__msa_srari_w((v4i32)sum_w, 2); in intra_predict_dc_tl_4x4_msa()
209 v4u32 sum_w; in intra_predict_dc_8x8_msa()
218 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d); in intra_predict_dc_8x8_msa()
220 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 4); in intra_predict_dc_8x8_msa()
235 v4u32 sum_w; in intra_predict_dc_tl_8x8_msa()
243 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_tl_8x8_msa()
268 v4u32 sum_w; in intra_predict_dc_16x16_msa()
[all …]
Davg_msa.c20 v4u32 sum = { 0 }; in vpx_avg_8x8_msa()
32 sum = (v4u32)__msa_srari_w((v4i32)sum, 6); in vpx_avg_8x8_msa()
43 v4u32 sum1; in vpx_avg_4x4_msa()
54 sum1 = (v4u32)__msa_srari_w((v4i32)sum2, 4); in vpx_avg_4x4_msa()
265 v4u32 tmp0_w = { 0 }; in vpx_satd_msa()
Dmacros_msa.h799 res0_m = __msa_hadd_u_d((v4u32)in, (v4u32)in); \
815 v4u32 res_m; \
/external/libvpx/libvpx/third_party/libyuv/source/
Dscale_msa.cc304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA()
343 reg0 = (v4u32)__msa_srari_w((v4i32)reg0, 4); in ScaleRowDown4Box_MSA()
344 reg1 = (v4u32)__msa_srari_w((v4i32)reg1, 4); in ScaleRowDown4Box_MSA()
345 reg2 = (v4u32)__msa_srari_w((v4i32)reg2, 4); in ScaleRowDown4Box_MSA()
346 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4); in ScaleRowDown4Box_MSA()
397 v4u32 tmp0, tmp1, tmp2, tmp3, tmp4; in ScaleRowDown38_2_Box_MSA()
401 v4u32 const_0x2AAA = (v4u32)__msa_fill_w(0x2AAA); in ScaleRowDown38_2_Box_MSA()
402 v4u32 const_0x4000 = (v4u32)__msa_fill_w(0x4000); in ScaleRowDown38_2_Box_MSA()
439 tmp0 = (v4u32)__msa_srai_w((v4i32)tmp0, 16); in ScaleRowDown38_2_Box_MSA()
440 tmp1 = (v4u32)__msa_srai_w((v4i32)tmp1, 16); in ScaleRowDown38_2_Box_MSA()
[all …]
Drow_msa.cc1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA()
1173 reg0 = (v4u32)__msa_ilvr_h(zero, (v8i16)vec0); in ARGBMultiplyRow_MSA()
1174 reg1 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec0); in ARGBMultiplyRow_MSA()
1175 reg2 = (v4u32)__msa_ilvr_h(zero, (v8i16)vec1); in ARGBMultiplyRow_MSA()
1176 reg3 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec1); in ARGBMultiplyRow_MSA()
1177 reg0 *= (v4u32)__msa_ilvr_h(zero, (v8i16)vec2); in ARGBMultiplyRow_MSA()
1178 reg1 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec2); in ARGBMultiplyRow_MSA()
1179 reg2 *= (v4u32)__msa_ilvr_h(zero, (v8i16)vec3); in ARGBMultiplyRow_MSA()
1180 reg3 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec3); in ARGBMultiplyRow_MSA()
1181 reg0 = (v4u32)__msa_srai_w((v4i32)reg0, 16); in ARGBMultiplyRow_MSA()
[all …]
/external/libyuv/files/source/
Dscale_msa.cc304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA()
343 reg0 = (v4u32)__msa_srari_w((v4i32)reg0, 4); in ScaleRowDown4Box_MSA()
344 reg1 = (v4u32)__msa_srari_w((v4i32)reg1, 4); in ScaleRowDown4Box_MSA()
345 reg2 = (v4u32)__msa_srari_w((v4i32)reg2, 4); in ScaleRowDown4Box_MSA()
346 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4); in ScaleRowDown4Box_MSA()
397 v4u32 tmp0, tmp1, tmp2, tmp3, tmp4; in ScaleRowDown38_2_Box_MSA()
401 v4u32 const_0x2AAA = (v4u32)__msa_fill_w(0x2AAA); in ScaleRowDown38_2_Box_MSA()
402 v4u32 const_0x4000 = (v4u32)__msa_fill_w(0x4000); in ScaleRowDown38_2_Box_MSA()
439 tmp0 = (v4u32)__msa_srai_w((v4i32)tmp0, 16); in ScaleRowDown38_2_Box_MSA()
440 tmp1 = (v4u32)__msa_srai_w((v4i32)tmp1, 16); in ScaleRowDown38_2_Box_MSA()
[all …]
Drow_msa.cc1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA()
1173 reg0 = (v4u32)__msa_ilvr_h(zero, (v8i16)vec0); in ARGBMultiplyRow_MSA()
1174 reg1 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec0); in ARGBMultiplyRow_MSA()
1175 reg2 = (v4u32)__msa_ilvr_h(zero, (v8i16)vec1); in ARGBMultiplyRow_MSA()
1176 reg3 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec1); in ARGBMultiplyRow_MSA()
1177 reg0 *= (v4u32)__msa_ilvr_h(zero, (v8i16)vec2); in ARGBMultiplyRow_MSA()
1178 reg1 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec2); in ARGBMultiplyRow_MSA()
1179 reg2 *= (v4u32)__msa_ilvr_h(zero, (v8i16)vec3); in ARGBMultiplyRow_MSA()
1180 reg3 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec3); in ARGBMultiplyRow_MSA()
1181 reg0 = (v4u32)__msa_srai_w((v4i32)reg0, 16); in ARGBMultiplyRow_MSA()
[all …]
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1049 "llvm.nvvm.tex.1d.v4u32.s32">;
1053 "llvm.nvvm.tex.1d.v4u32.f32">;
1057 "llvm.nvvm.tex.1d.level.v4u32.f32">;
1062 "llvm.nvvm.tex.1d.grad.v4u32.f32">;
1103 "llvm.nvvm.tex.1d.array.v4u32.s32">;
1107 "llvm.nvvm.tex.1d.array.v4u32.f32">;
1112 "llvm.nvvm.tex.1d.array.level.v4u32.f32">;
1117 "llvm.nvvm.tex.1d.array.grad.v4u32.f32">;
1158 "llvm.nvvm.tex.2d.v4u32.s32">;
1162 "llvm.nvvm.tex.2d.v4u32.f32">;
[all …]
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1347 "llvm.nvvm.tex.1d.v4u32.s32">;
1351 "llvm.nvvm.tex.1d.v4u32.f32">;
1355 "llvm.nvvm.tex.1d.level.v4u32.f32">;
1360 "llvm.nvvm.tex.1d.grad.v4u32.f32">;
1401 "llvm.nvvm.tex.1d.array.v4u32.s32">;
1405 "llvm.nvvm.tex.1d.array.v4u32.f32">;
1410 "llvm.nvvm.tex.1d.array.level.v4u32.f32">;
1415 "llvm.nvvm.tex.1d.array.grad.v4u32.f32">;
1456 "llvm.nvvm.tex.2d.v4u32.s32">;
1460 "llvm.nvvm.tex.2d.v4u32.f32">;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1354 "llvm.nvvm.tex.1d.v4u32.s32">;
1358 "llvm.nvvm.tex.1d.v4u32.f32">;
1362 "llvm.nvvm.tex.1d.level.v4u32.f32">;
1367 "llvm.nvvm.tex.1d.grad.v4u32.f32">;
1408 "llvm.nvvm.tex.1d.array.v4u32.s32">;
1412 "llvm.nvvm.tex.1d.array.v4u32.f32">;
1417 "llvm.nvvm.tex.1d.array.level.v4u32.f32">;
1422 "llvm.nvvm.tex.1d.array.grad.v4u32.f32">;
1463 "llvm.nvvm.tex.2d.v4u32.s32">;
1467 "llvm.nvvm.tex.2d.v4u32.f32">;
[all …]
/external/llvm-project/clang/test/CodeGen/
Dbuiltins-mips-msa-error.c26 v4u32 v4u32_a = (v4u32) {0, 1, 2, 3}; in test()
27 v4u32 v4u32_r; in test()
Dbuiltins-mips-msa.c30 v4u32 v4u32_a = (v4u32) {0, 1, 2, 3}; in test()
31 v4u32 v4u32_b = (v4u32) {1, 2, 3, 4}; in test()
32 v4u32 v4u32_r; in test()
/external/clang/test/CodeGen/
Dbuiltins-mips-msa.c11 typedef unsigned int v4u32 __attribute__ ((vector_size(16))); typedef
37 v4u32 v4u32_a = (v4u32) {0, 1, 2, 3}; in test()
38 v4u32 v4u32_b = (v4u32) {1, 2, 3, 4}; in test()
39 v4u32 v4u32_r; in test()
/external/deqp/external/vulkancts/modules/vulkan/robustness/
DvktRobustBufferAccessWithVariablePointersTests.cpp746 , v4u32(autoincrement) in Variables()
789 const Variable v4u32; member in vkt::robustness::__anonebaadb960111::Variables
988 (var.v4u32, is, op::TypeVector, var.u32, 4); in MakeShader()
1008 shaderSource.makeSame(var.buffer_type_vec, var.v4u32); in MakeShader()
/external/llvm-project/clang/lib/Headers/
Dmsa.h24 typedef unsigned int v4u32 __attribute__((vector_size(16), aligned(16))); typedef
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3602 nvvm_tex_1d_array_grad_v4u32_f32, // llvm.nvvm.tex.1d.array.grad.v4u32.f32
3605 nvvm_tex_1d_array_level_v4u32_f32, // llvm.nvvm.tex.1d.array.level.v4u32.f32
3610 nvvm_tex_1d_array_v4u32_f32, // llvm.nvvm.tex.1d.array.v4u32.f32
3611 nvvm_tex_1d_array_v4u32_s32, // llvm.nvvm.tex.1d.array.v4u32.s32
3614 nvvm_tex_1d_grad_v4u32_f32, // llvm.nvvm.tex.1d.grad.v4u32.f32
3617 nvvm_tex_1d_level_v4u32_f32, // llvm.nvvm.tex.1d.level.v4u32.f32
3622 nvvm_tex_1d_v4u32_f32, // llvm.nvvm.tex.1d.v4u32.f32
3623 nvvm_tex_1d_v4u32_s32, // llvm.nvvm.tex.1d.v4u32.s32
3626 nvvm_tex_2d_array_grad_v4u32_f32, // llvm.nvvm.tex.2d.array.grad.v4u32.f32
3629 nvvm_tex_2d_array_level_v4u32_f32, // llvm.nvvm.tex.2d.array.level.v4u32.f32
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3602 nvvm_tex_1d_array_grad_v4u32_f32, // llvm.nvvm.tex.1d.array.grad.v4u32.f32
3605 nvvm_tex_1d_array_level_v4u32_f32, // llvm.nvvm.tex.1d.array.level.v4u32.f32
3610 nvvm_tex_1d_array_v4u32_f32, // llvm.nvvm.tex.1d.array.v4u32.f32
3611 nvvm_tex_1d_array_v4u32_s32, // llvm.nvvm.tex.1d.array.v4u32.s32
3614 nvvm_tex_1d_grad_v4u32_f32, // llvm.nvvm.tex.1d.grad.v4u32.f32
3617 nvvm_tex_1d_level_v4u32_f32, // llvm.nvvm.tex.1d.level.v4u32.f32
3622 nvvm_tex_1d_v4u32_f32, // llvm.nvvm.tex.1d.v4u32.f32
3623 nvvm_tex_1d_v4u32_s32, // llvm.nvvm.tex.1d.v4u32.s32
3626 nvvm_tex_2d_array_grad_v4u32_f32, // llvm.nvvm.tex.2d.array.grad.v4u32.f32
3629 nvvm_tex_2d_array_level_v4u32_f32, // llvm.nvvm.tex.2d.array.level.v4u32.f32
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3602 nvvm_tex_1d_array_grad_v4u32_f32, // llvm.nvvm.tex.1d.array.grad.v4u32.f32
3605 nvvm_tex_1d_array_level_v4u32_f32, // llvm.nvvm.tex.1d.array.level.v4u32.f32
3610 nvvm_tex_1d_array_v4u32_f32, // llvm.nvvm.tex.1d.array.v4u32.f32
3611 nvvm_tex_1d_array_v4u32_s32, // llvm.nvvm.tex.1d.array.v4u32.s32
3614 nvvm_tex_1d_grad_v4u32_f32, // llvm.nvvm.tex.1d.grad.v4u32.f32
3617 nvvm_tex_1d_level_v4u32_f32, // llvm.nvvm.tex.1d.level.v4u32.f32
3622 nvvm_tex_1d_v4u32_f32, // llvm.nvvm.tex.1d.v4u32.f32
3623 nvvm_tex_1d_v4u32_s32, // llvm.nvvm.tex.1d.v4u32.s32
3626 nvvm_tex_2d_array_grad_v4u32_f32, // llvm.nvvm.tex.2d.array.grad.v4u32.f32
3629 nvvm_tex_2d_array_level_v4u32_f32, // llvm.nvvm.tex.2d.array.level.v4u32.f32
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3602 nvvm_tex_1d_array_grad_v4u32_f32, // llvm.nvvm.tex.1d.array.grad.v4u32.f32
3605 nvvm_tex_1d_array_level_v4u32_f32, // llvm.nvvm.tex.1d.array.level.v4u32.f32
3610 nvvm_tex_1d_array_v4u32_f32, // llvm.nvvm.tex.1d.array.v4u32.f32
3611 nvvm_tex_1d_array_v4u32_s32, // llvm.nvvm.tex.1d.array.v4u32.s32
3614 nvvm_tex_1d_grad_v4u32_f32, // llvm.nvvm.tex.1d.grad.v4u32.f32
3617 nvvm_tex_1d_level_v4u32_f32, // llvm.nvvm.tex.1d.level.v4u32.f32
3622 nvvm_tex_1d_v4u32_f32, // llvm.nvvm.tex.1d.v4u32.f32
3623 nvvm_tex_1d_v4u32_s32, // llvm.nvvm.tex.1d.v4u32.s32
3626 nvvm_tex_2d_array_grad_v4u32_f32, // llvm.nvvm.tex.2d.array.grad.v4u32.f32
3629 nvvm_tex_2d_array_level_v4u32_f32, // llvm.nvvm.tex.2d.array.level.v4u32.f32
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3596 nvvm_tex_1d_array_grad_v4u32_f32, // llvm.nvvm.tex.1d.array.grad.v4u32.f32
3599 nvvm_tex_1d_array_level_v4u32_f32, // llvm.nvvm.tex.1d.array.level.v4u32.f32
3604 nvvm_tex_1d_array_v4u32_f32, // llvm.nvvm.tex.1d.array.v4u32.f32
3605 nvvm_tex_1d_array_v4u32_s32, // llvm.nvvm.tex.1d.array.v4u32.s32
3608 nvvm_tex_1d_grad_v4u32_f32, // llvm.nvvm.tex.1d.grad.v4u32.f32
3611 nvvm_tex_1d_level_v4u32_f32, // llvm.nvvm.tex.1d.level.v4u32.f32
3616 nvvm_tex_1d_v4u32_f32, // llvm.nvvm.tex.1d.v4u32.f32
3617 nvvm_tex_1d_v4u32_s32, // llvm.nvvm.tex.1d.v4u32.s32
3620 nvvm_tex_2d_array_grad_v4u32_f32, // llvm.nvvm.tex.2d.array.grad.v4u32.f32
3623 nvvm_tex_2d_array_level_v4u32_f32, // llvm.nvvm.tex.2d.array.level.v4u32.f32
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc5111 "llvm.nvvm.tex.1d.array.grad.v4u32.f32",
5114 "llvm.nvvm.tex.1d.array.level.v4u32.f32",
5119 "llvm.nvvm.tex.1d.array.v4u32.f32",
5120 "llvm.nvvm.tex.1d.array.v4u32.s32",
5123 "llvm.nvvm.tex.1d.grad.v4u32.f32",
5126 "llvm.nvvm.tex.1d.level.v4u32.f32",
5131 "llvm.nvvm.tex.1d.v4u32.f32",
5132 "llvm.nvvm.tex.1d.v4u32.s32",
5135 "llvm.nvvm.tex.2d.array.grad.v4u32.f32",
5138 "llvm.nvvm.tex.2d.array.level.v4u32.f32",
[all …]

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