| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 96 v5i32 = 47, // 5 x i32 enumerator
479 case v5i32: in getVectorElementType()
614 case v5i32: in getVectorNumElements()
774 case v5i32: in getSizeInBits()
962 if (NumElements == 5) return MVT::v5i32; in getVectorVT()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 41 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
82 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
212 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
|
| D | SIRegisterInfo.td | 719 def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
724 def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
803 def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
819 def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>;
|
| D | SIInstructions.td | 1024 i32, v5i32, Index, !cast<SubRegIndex>(sub#Index)
1027 i32, v5i32, Index, !cast<SubRegIndex>(sub#Index)
1188 def : BitConvert <v5i32, v5f32, SGPR_160>;
1189 def : BitConvert <v5f32, v5i32, SGPR_160>;
|
| D | AMDGPUISelLowering.cpp | 87 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
207 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
334 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
345 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
423 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32 in AMDGPUTargetLowering()
514 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
|
| D | SIISelLowering.cpp | 148 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass); in SITargetLowering()
193 setOperationAction(ISD::LOAD, MVT::v5i32, Custom); in SITargetLowering()
202 setOperationAction(ISD::STORE, MVT::v5i32, Custom); in SITargetLowering()
418 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom); in SITargetLowering()
|
| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 97 v5i32 = 48, // 5 x i32 enumerator
548 case v5i32: in getVectorElementType()
727 case v5i32: in getVectorNumElements()
908 case v5i32: in getSizeInBits()
1149 if (NumElements == 5) return MVT::v5i32; in getVectorVT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 124 CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
|
| D | SIRegisterInfo.td | 539 def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
544 def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
624 def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
|
| D | SIInstructions.td | 882 i32, v5i32, Index, !cast<SubRegIndex>(sub#Index)
885 i32, v5i32, Index, !cast<SubRegIndex>(sub#Index)
1044 def : BitConvert <v5i32, v5f32, SGPR_160>;
1045 def : BitConvert <v5f32, v5i32, SGPR_160>;
|
| D | AMDGPUISelLowering.cpp | 83 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
183 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
293 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
357 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32 in AMDGPUTargetLowering()
448 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
|
| D | SIISelLowering.cpp | 141 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass); in SITargetLowering()
179 setOperationAction(ISD::LOAD, MVT::v5i32, Custom); in SITargetLowering()
188 setOperationAction(ISD::STORE, MVT::v5i32, Custom); in SITargetLowering()
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom); in SITargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 192 case MVT::v5i32: return VectorType::get(Type::getInt32Ty(Context), 5); in getTypeForEVT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 71 def v5i32 : ValueType<160, 47>; // 5 x i32 vector value
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 73 def v5i32 : ValueType<160, 48>; // 5 x i32 vector value
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 264 case MVT::v5i32: in getTypeForEVT()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 114 case MVT::v5i32: return "MVT::v5i32"; in getEnumName()
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | oddshuffles.ll | 140 define void @v5i32(<4 x i32> %a, <4 x i32> %b, <5 x i32>* %p) nounwind {
141 ; SSE2-LABEL: v5i32:
150 ; SSE42-LABEL: v5i32:
159 ; AVX1-LABEL: v5i32:
168 ; AVX2-LABEL: v5i32:
177 ; XOP-LABEL: v5i32:
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | usubsat.ll | 1197 %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
1272 %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
3741 declare <5 x i32> @llvm.usub.sat.v5i32(<5 x i32>, <5 x i32>) #0
|
| D | uaddsat.ll | 1242 %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
1322 %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
3871 declare <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32>, <5 x i32>) #0
|
| D | ssubsat.ll | 1925 %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
2084 %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
7272 declare <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32>, <5 x i32>) #0
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| D | saddsat.ll | 1939 %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
2098 %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
7286 declare <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32>, <5 x i32>) #0
|