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/external/llvm-project/llvm/test/MC/AArch64/
Dneon-simd-misc.s11 rev64 v6.4s, v8.4s
117 suqadd v6.4s, v8.4s
118 suqadd v6.2d, v8.2d
137 usqadd v6.4s, v8.4s
138 usqadd v6.2d, v8.2d
157 sqabs v6.4s, v8.4s
158 sqabs v6.2d, v8.2d
177 sqneg v6.4s, v8.4s
178 sqneg v6.2d, v8.2d
197 abs v6.4s, v8.4s
[all …]
Darm64-simd-ldst.s11 ld1.8b {v4, v5, v6}, [x3]
102 ; CHECK: ld1.8b { v4, v5, v6 }, [x3] ; encoding: [0x64,0x60,0x40,0x0c]
223 ld3.8b {v4, v5, v6}, [x19]
224 ld3.16b {v4, v5, v6}, [x19]
225 ld3.4h {v4, v5, v6}, [x19]
226 ld3.8h {v4, v5, v6}, [x19]
227 ld3.2s {v4, v5, v6}, [x19]
228 ld3.4s {v4, v5, v6}, [x19]
229 ld3.2d {v4, v5, v6}, [x19]
236 ld3.4s {v4, v5, v6}, [x29]
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s11 rev64 v6.4s, v8.4s
117 suqadd v6.4s, v8.4s
118 suqadd v6.2d, v8.2d
137 usqadd v6.4s, v8.4s
138 usqadd v6.2d, v8.2d
157 sqabs v6.4s, v8.4s
158 sqabs v6.2d, v8.2d
177 sqneg v6.4s, v8.4s
178 sqneg v6.2d, v8.2d
197 abs v6.4s, v8.4s
[all …]
Darm64-simd-ldst.s11 ld1.8b {v4, v5, v6}, [x3]
102 ; CHECK: ld1.8b { v4, v5, v6 }, [x3] ; encoding: [0x64,0x60,0x40,0x0c]
223 ld3.8b {v4, v5, v6}, [x19]
224 ld3.16b {v4, v5, v6}, [x19]
225 ld3.4h {v4, v5, v6}, [x19]
226 ld3.8h {v4, v5, v6}, [x19]
227 ld3.2s {v4, v5, v6}, [x19]
228 ld3.4s {v4, v5, v6}, [x19]
229 ld3.2d {v4, v5, v6}, [x19]
236 ld3.4s {v4, v5, v6}, [x29]
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs4 0x06,0x09,0xa0,0x4e = rev64 v6.4s, v8.4s
40 0x06,0x39,0xa0,0x4e = suqadd v6.4s, v8.4s
41 0x06,0x39,0xe0,0x4e = suqadd v6.2d, v8.2d
47 0x06,0x39,0xa0,0x6e = usqadd v6.4s, v8.4s
48 0x06,0x39,0xe0,0x6e = usqadd v6.2d, v8.2d
54 0x06,0x79,0xa0,0x4e = sqabs v6.4s, v8.4s
55 0x06,0x79,0xe0,0x4e = sqabs v6.2d, v8.2d
61 0x06,0x79,0xa0,0x6e = sqneg v6.4s, v8.4s
62 0x06,0x79,0xe0,0x6e = sqneg v6.2d, v8.2d
68 0x06,0xb9,0xa0,0x4e = abs v6.4s, v8.4s
[all …]
/external/libavc/common/armv8/
Dih264_weighted_pred_av8.s141 ld1 {v6.s}[0], [x0], x2 //load row 3 in source
142 ld1 {v6.s}[1], [x0], x2 //load row 4 in source
145 uxtl v6.8h, v6.8b //converting rows 3,4 to 16-bit
148 mul v6.8h, v6.8h , v2.h[0] //weight mult. for rows 3,4
152 srshl v6.8h, v6.8h , v0.8h //rounds off the weighted samples from rows 3,4
155 saddw v6.8h, v6.8h , v3.8b //adding offset for rows 3,4
158 sqxtun v6.8b, v6.8h //saturating rows 3,4 to unsigned 8-bit
162 st1 {v6.s}[0], [x1], x3 //store row 3 in destination
163 st1 {v6.s}[1], [x1], x3 //store row 4 in destination
172 ld1 {v6.8b}, [x0], x2 //load row 2 in source
[all …]
Dih264_inter_pred_filters_luma_horz_av8.s133 ld1 {v5.8b, v6.8b, v7.8b}, [x0], x2 //// Load row1
136 ext v28.8b, v5.8b , v6.8b, #5 ////extract a[5] (column1,row1)
138 ext v27.8b, v6.8b , v7.8b, #5 ////extract a[5] (column2,row1)
141 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
144 ext v28.8b, v5.8b , v6.8b, #2 ////extract a[2] (column1,row1)
146 ext v27.8b, v6.8b , v7.8b, #2 ////extract a[2] (column2,row1)
152 ext v28.8b, v5.8b , v6.8b, #3 ////extract a[3] (column1,row1)
154 ext v27.8b, v6.8b , v7.8b, #3 ////extract a[3] (column2,row1)
160 ext v28.8b, v5.8b , v6.8b, #1 ////extract a[1] (column1,row1)
162 ext v27.8b, v6.8b , v7.8b, #1 ////extract a[1] (column2,row1)
[all …]
Dih264_inter_pred_luma_horz_qpel_av8.s141 ld1 {v5.8b, v6.8b, v7.8b}, [x0], x2 //// Load row1
144 ext v28.8b, v5.8b , v6.8b , #5
146 ext v27.8b, v6.8b , v7.8b , #5
149 uaddl v16.8h, v27.8b, v6.8b //// a0 + a5 (column2,row1)
152 ext v28.8b, v5.8b , v6.8b , #2
154 ext v27.8b, v6.8b , v7.8b , #2
160 ext v28.8b, v5.8b , v6.8b , #3
162 ext v27.8b, v6.8b , v7.8b , #3
168 ext v28.8b, v5.8b , v6.8b , #1
170 ext v27.8b, v6.8b , v7.8b , #1
[all …]
Dih264_padding_neon_av8.s198 dup v6.16b, w11
202 st1 {v6.16b}, [x4], x1 // 16 bytes store
214 dup v6.16b, w11
217 st1 {v6.16b}, [x4], x1 // 16 bytes store
238 dup v6.16b, w11
242 st1 {v6.16b}, [x4], #16 // 16 bytes store
246 st1 {v6.16b}, [x4], x6 // 16 bytes store
258 dup v6.16b, w11
261 st1 {v6.16b}, [x4], #16 // 16 bytes store
262 st1 {v6.16b}, [x4], x6 // 16 bytes store
[all …]
/external/llvm/test/MC/AMDGPU/
Dvop3.s13 v_cmp_lt_f32_e64 s[2:3], v4, -v6
19 v_cmp_lt_f32_e64 vcc, v4, v6
27 v_cmp_lt_f32 s[2:3] -v4, v6
31 v_cmp_lt_f32 s[2:3] v4, -v6
35 v_cmp_lt_f32 s[2:3] -v4, -v6
39 v_cmp_lt_f32 s[2:3] |v4|, v6
43 v_cmp_lt_f32 s[2:3] v4, |v6|
47 v_cmp_lt_f32 s[2:3] |v4|, |v6|
51 v_cmp_lt_f32 s[2:3] -|v4|, v6
55 v_cmp_lt_f32 s[2:3] -abs(v4), v6
[all …]
Dds.s25 ds_write2_b32 v2, v4, v6 offset0:4
29 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
33 ds_write2_b32 v2, v4, v6 offset1:8
101 ds_mskor_b32 v2, v4, v6
109 ds_write2_b32 v2, v4, v6
113 ds_write2st64_b32 v2, v4, v6
117 ds_cmpst_b32 v2, v4, v6
121 ds_cmpst_f32 v2, v4, v6
125 ds_min_f32 v2, v4, v6
129 ds_max_f32 v2, v4, v6
[all …]
/external/parameter-framework/asio-1.10.6/include/asio/ip/detail/impl/
Dendpoint.ipp49 data_.v6.sin6_family = ASIO_OS_DEF(AF_INET6);
50 data_.v6.sin6_port =
52 data_.v6.sin6_flowinfo = 0;
53 data_.v6.sin6_addr.s6_addr[0] = 0; data_.v6.sin6_addr.s6_addr[1] = 0;
54 data_.v6.sin6_addr.s6_addr[2] = 0, data_.v6.sin6_addr.s6_addr[3] = 0;
55 data_.v6.sin6_addr.s6_addr[4] = 0, data_.v6.sin6_addr.s6_addr[5] = 0;
56 data_.v6.sin6_addr.s6_addr[6] = 0, data_.v6.sin6_addr.s6_addr[7] = 0;
57 data_.v6.sin6_addr.s6_addr[8] = 0, data_.v6.sin6_addr.s6_addr[9] = 0;
58 data_.v6.sin6_addr.s6_addr[10] = 0, data_.v6.sin6_addr.s6_addr[11] = 0;
59 data_.v6.sin6_addr.s6_addr[12] = 0, data_.v6.sin6_addr.s6_addr[13] = 0;
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsdiv.i32.ll27 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
30 ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
165 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
170 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6
172 ; GISEL-NEXT: v_xor_b32_e32 v9, v6, v7
175 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
179 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
182 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
184 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
186 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
[all …]
Dudiv.i32.ll129 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
132 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
134 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
136 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
138 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6
140 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
142 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7
145 ; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2
149 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
153 ; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
[all …]
Durem.i64.ll21 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
31 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v5
32 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v4
34 ; CHECK-NEXT: v_mul_hi_u32 v11, v6, v4
61 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v4
63 ; CHECK-NEXT: v_mul_hi_u32 v10, v6, v4
64 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9
68 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6
69 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10
70 ; CHECK-NEXT: v_mul_lo_u32 v7, v4, v6
[all …]
Dsrem.i32.ll153 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
157 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6
161 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
198 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
200 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
208 ; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
212 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
216 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
261 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
263 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
[all …]
Dudiv.i64.ll21 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
31 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v5
32 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v4
34 ; CHECK-NEXT: v_mul_hi_u32 v11, v6, v4
61 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v4
63 ; CHECK-NEXT: v_mul_hi_u32 v10, v6, v4
64 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9
68 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6
69 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10
70 ; CHECK-NEXT: v_mul_lo_u32 v7, v4, v6
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbypass-div.ll25 ; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v4
30 ; GFX9-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
31 ; GFX9-NEXT: v_rcp_f32_e32 v6, v6
33 ; GFX9-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
34 ; GFX9-NEXT: v_mul_f32_e32 v7, 0x2f800000, v6
36 ; GFX9-NEXT: v_mac_f32_e32 v6, 0xcf800000, v7
37 ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
39 ; GFX9-NEXT: v_mul_lo_u32 v10, v9, v6
40 ; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6
42 ; GFX9-NEXT: v_mul_lo_u32 v13, v8, v6
[all …]
/external/libhevc/common/arm64/
Dihevc_padding.s113 dup v6.16b,w11
141 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
142 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
143 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
144 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
145 st1 {v6.16b},[x7] //128/8 = 16 bytes store
231 dup v6.8h,w11
259 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
260 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
261 st1 {v6.16b},[x7],#16 //128/8 = 16 bytes store
[all …]
Dihevc_intra_pred_luma_planar.s147 dup v6.8b,w9 //nt - 1 - row
190 umlal v27.8h, v6.8b, v3.8b //(1)(nt-1-row) * src[2nt+1+col]
198 sub v6.8b, v6.8b , v7.8b //(1)
206 umlal v30.8h, v6.8b, v3.8b //(2)
212 sub v6.8b, v6.8b , v7.8b //(2)
221 umlal v28.8h, v6.8b, v3.8b //(3)
229 sub v6.8b, v6.8b , v7.8b //(3)
238 umlal v25.8h, v6.8b, v3.8b //(4)
246 sub v6.8b, v6.8b , v7.8b //(4)
255 umlal v16.8h, v6.8b, v3.8b //(5)
[all …]
/external/libnetfilter_conntrack/src/conntrack/
Dobjopt.c30 memcpy(&this->src.v6, &other->dst.v6, sizeof(union __nfct_address)); in __autocomplete()
31 memcpy(&this->dst.v6, &other->src.v6, sizeof(union __nfct_address)); in __autocomplete()
63 memcpy(&ct->snat.min_ip.v6, &ct->repl.dst.v6, in setobjopt_undo_snat()
65 memcpy(&ct->snat.max_ip.v6, &ct->snat.min_ip.v6, in setobjopt_undo_snat()
67 memcpy(&ct->repl.dst.v6, &ct->head.orig.src.v6, in setobjopt_undo_snat()
85 memcpy(&ct->dnat.min_ip.v6, &ct->repl.src.v6, in setobjopt_undo_dnat()
87 memcpy(&ct->dnat.max_ip.v6, &ct->dnat.min_ip.v6, in setobjopt_undo_dnat()
89 memcpy(&ct->repl.src.v6, &ct->head.orig.dst.v6, in setobjopt_undo_dnat()
156 if (memcmp(&ct->repl.dst.v6, &ct->head.orig.src.v6, in getobjopt_is_snat()
178 if (memcmp(&ct->repl.src.v6, &ct->head.orig.dst.v6, in getobjopt_is_dnat()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Daggr-licm.ll26 %v6 = phi i32 [ 0, %b0 ], [ %v198, %b1 ]
28 %v8 = zext i32 %v6 to i64
31 %v11 = add nuw nsw i32 %v6, 32
38 %v18 = add nuw nsw i32 %v6, 1
43 %v23 = add nsw i32 %v6, 33
50 %v30 = add nsw i32 %v6, 2
55 %v35 = add nsw i32 %v6, 34
62 %v42 = add nsw i32 %v6, 3
67 %v47 = add nsw i32 %v6, 35
74 %v54 = add nsw i32 %v6, 4
[all …]
Dmul64-sext.ll12 %v6 = ashr exact i64 %v5, 32
13 %v7 = mul nsw i64 %v6, %v4
26 %v6 = ashr exact i64 %v5, 32
27 %v7 = mul nsw i64 %v6, %v4
40 %v6 = ashr exact i64 %v5, 48
41 %v7 = mul nsw i64 %v6, %v4
54 %v6 = sext i32 %v5 to i64
55 %v7 = mul nsw i64 %v3, %v6
67 %v6 = shl i64 %a1, 32
68 %v7 = ashr exact i64 %v6, 32
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_inv_dit_fft_8pt.s42 LD1 {v6.s}[0], [x6], x5
44 LD1 {v6.s}[1], [x6], x5
60 SQADD v10.2s, v2.2s, v6.2s //a20_v = vqadd_s32(y1_3,y9_11);
65 SQSUB v5.2s, v2.2s, v6.2s //a3_v = vqsub_s32(y1_3,y9_11);
67 SQSUB v6.2s, v4.2s, v8.2s //a1_v = vqsub_s32(y5_7,y13_15);
75 SQADD v9.2s, v1.2s, v6.2s //x6_14 = vqadd_s32(a0_v,a1_v);
77 SQSUB v10.2s, v1.2s, v6.2s //x2_10 = vqsub_s32(a0_v,a1_v);
83 UZP1 v6.2s, v4.2s, v8.2s //x4_5 = vuzp1_s32(x4_12,x5_13);
90 SQADD v12.2s, v6.2s, v7.2s //real_imag4 = vqadd_s32(x4_5,x13_12);
91 SQSUB v14.2s, v6.2s, v7.2s //a0_1_v = vqsub_s32(x4_5,x13_12);
[all …]
/external/rust/crates/ring/pregenerated/
Daesv8-armx-ios64.S64 tbl v6.16b,{v3.16b},v2.16b
67 aese v6.16b,v0.16b
74 eor v6.16b,v6.16b,v1.16b
77 eor v3.16b,v3.16b,v6.16b
82 tbl v6.16b,{v3.16b},v2.16b
85 aese v6.16b,v0.16b
91 eor v6.16b,v6.16b,v1.16b
94 eor v3.16b,v3.16b,v6.16b
96 tbl v6.16b,{v3.16b},v2.16b
99 aese v6.16b,v0.16b
[all …]

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