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Searched refs:v_add_co_u32_e64 (Results 1 – 25 of 34) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Doffset-split-global.ll60 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
84 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x1800, v0
126 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
150 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
172 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
196 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x1800, v0
220 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x3800, v0
242 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
266 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
290 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xffffc000, v0
[all …]
Doffset-split-flat.ll20 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, 1
42 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x7ff, v0
64 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
88 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
112 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfffff800, v0
136 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
160 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
182 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
206 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
230 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, 0x3fff, v0
[all …]
Dglobal-saddr-load.ll88 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
114 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
140 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
244 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0xfffff800, s2
267 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0xfffff800, s2
304 ; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2
312 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0, s2
328 ; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2
336 ; GFX10-NEXT: v_add_co_u32_e64 v0, s[0:1], 0, s2
352 ; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2
[all …]
Dshl_add_ptr_csub.ll6 ; GCN: v_add_co_u32_e64 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
Dmemory-legalizer-flat-nontemporal.ll87 ; GFX10-WGP-NEXT: v_add_co_u32_e64 v0, s0, s0, v0
101 ; GFX10-CU-NEXT: v_add_co_u32_e64 v0, s0, s0, v0
215 ; GFX10-WGP-NEXT: v_add_co_u32_e64 v0, s0, s2, v0
229 ; GFX10-CU-NEXT: v_add_co_u32_e64 v0, s0, s2, v0
Dvgpr-descriptor-waterfall-loop-idom-update.ll12 ; GCN-NEXT: v_add_co_u32_e64 v2, vcc_lo, v0, 8
Dexpand-scalar-carry-out-select-user.ll30 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
48 ; GFX10-NEXT: v_add_co_u32_e64 v0, s5, s4, s4
Dcarryout-selection.ll54 ; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
84 ; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}}
128 ; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
173 ; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
Dbypass-div.ll57 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[4:5], v6, v10
119 ; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 2, v6
122 ; GFX9-NEXT: v_add_co_u32_e64 v14, s[4:5], 1, v6
218 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8
275 ; GFX9-NEXT: v_add_co_u32_e64 v9, s[4:5], 2, v4
278 ; GFX9-NEXT: v_add_co_u32_e64 v11, s[4:5], 1, v4
375 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v9
532 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8
812 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v10
873 ; GFX9-NEXT: v_add_co_u32_e64 v15, s[6:7], 2, v4
[all …]
Dwave32.ll286 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}}
288 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, s{{[0-9]+}}
331 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
334 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
335 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
336 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
341 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}}
344 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
345 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
346 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
Dgfx10-vop-literal.ll5 ; GFX10: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, 0x80992bff, v{{[0-9]+}}
Didiv-licm.ll253 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
313 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s6, v5
358 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5
425 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s6, v5
Dflat-address-space.ll194 ; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
223 ; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
Dmul24-pass-ordering.ll92 ; GFX9-NEXT: v_add_co_u32_e64 v8, s[6:7], v10, v8
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dwave32.txt48 # GFX1032: v_add_co_u32_e64 v2, vcc_lo, s0, v2
49 # GFX1064: v_add_co_u32_e64 v2, vcc, s0, v2
110 # GFX1032: v_add_co_u32_e64 v0, s0, v0, v2
111 # GFX1064: v_add_co_u32_e64 v0, s[0:1], v0, v2
/external/llvm-project/llvm/test/MC/AMDGPU/
Dlds_direct.s57 v_add_co_u32_e64 v0, s[0:1], src_lds_direct, v0 label
Dwave_any.s132 v_add_co_u32_e64 v0, s0, v0, v2 label
165 v_add_co_u32_e64 v0, s[0:1], v0, v2 label
Dwave32.s302 v_add_co_u32_e64 v0, s0, v0, v2 label
338 v_add_co_u32_e64 v0, s[0:1], v0, v2 label
Dgfx8_unsupported.s700 v_add_co_u32_e64 v0, s0, v0, v2 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.global.atomic.csub.ll26 ; GCN-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, v3
57 ; GCN-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, v3
Dsaddsat.ll4678 ; GFX9-NEXT: v_add_co_u32_e64 v2, s[6:7], 0, v0
4689 ; GFX10-NEXT: v_add_co_u32_e64 v10, vcc_lo, v0, v2
4694 ; GFX10-NEXT: v_add_co_u32_e64 v0, s5, v6, 0
4858 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[2:3], 0, v0
4867 ; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, s0, v0
4872 ; GFX10-NEXT: v_add_co_u32_e64 v0, s1, v4, 0
4925 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], 0, v0
4934 ; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, v0, s0
4939 ; GFX10-NEXT: v_add_co_u32_e64 v0, s0, v4, 0
5012 ; GFX9-NEXT: v_add_co_u32_e64 v1, s[6:7], 0, v0
[all …]
Duaddsat.ll2653 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, v2
2768 ; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, s0, v0
2812 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, s0
2877 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, v10
2879 ; GFX10-NEXT: v_add_co_u32_e64 v5, vcc_lo, v2, v15
3257 ; GFX10-NEXT: v_add_co_u32_e64 v10, vcc_lo, s0, v0
3351 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, s0
3494 ; GFX10-NEXT: v_add_co_u32_e64 v0, vcc_lo, v0, v18
3503 ; GFX10-NEXT: v_add_co_u32_e64 v4, vcc_lo, v4, v10
Dssubsat.ll4664 ; GFX9-NEXT: v_add_co_u32_e64 v2, s[6:7], 0, v0
4680 ; GFX10-NEXT: v_add_co_u32_e64 v0, s5, v6, 0
4844 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[2:3], 0, v0
4858 ; GFX10-NEXT: v_add_co_u32_e64 v0, s1, v4, 0
4911 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], 0, v0
4925 ; GFX10-NEXT: v_add_co_u32_e64 v0, s0, v4, 0
4998 ; GFX9-NEXT: v_add_co_u32_e64 v1, s[6:7], 0, v0
5008 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[6:7], 0, v2
5032 ; GFX10-NEXT: v_add_co_u32_e64 v1, s5, v12, 0
5035 ; GFX10-NEXT: v_add_co_u32_e64 v2, s7, v0, 0
[all …]
/external/mesa3d/docs/relnotes/
D20.0.1.rst160 - aco: fix carry-out size for wave32 v_add_co_u32_e64
/external/mesa3d/src/amd/compiler/
Daco_optimizer.cpp541 case aco_opcode::v_add_co_u32_e64: in can_swap_operands()
749 case aco_opcode::v_add_co_u32_e64: in parse_base_offset()
1401 case aco_opcode::v_add_co_u32_e64: in label_instruction()
2873 instr->opcode == aco_opcode::v_add_co_u32_e64) { in combine_instruction()

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