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Searched refs:v_add_i32 (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dadd_i64.ll7 ; SI: v_add_i32
22 ; SI: v_add_i32
35 ; SI: v_add_i32
57 ; SI: v_add_i32
59 ; SI: v_add_i32
Dsminmax.ll22 ; GCN: v_add_i32
63 ; GCN: v_add_i32
64 ; GCN: v_add_i32
126 ; GCN: v_add_i32
127 ; GCN: v_add_i32
128 ; GCN: v_add_i32
129 ; GCN: v_add_i32
Duaddo.ll40 ; SI: v_add_i32
71 ; SI: v_add_i32
Dmove-addr64-rsrc-dead-subreg-writes.ll6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
Dllvm.AMDGPU.bfe.u32.ll77 ; SI: v_add_i32
92 ; SI: v_add_i32
107 ; SI: v_add_i32
121 ; SI: v_add_i32
136 ; SI: v_add_i32
151 ; SI: v_add_i32
Dsdiv.ll40 ; SI: v_add_i32
43 ; SI: v_add_i32
Dextractelt-to-trunc.ll34 ; GCN: v_add_i32
Dsaddo.ll52 ; SI: v_add_i32
Dsplit-scalar-i64-add.ll36 ; SI: v_add_i32
Dlocal-stack-slot-bug.ll4 ; This used to fail due to a v_add_i32 instruction with an illegal immediate
/external/llvm/test/MC/AMDGPU/regression/
Dbug28413.s28 v_add_i32 v0, vcc, 0.5, v0 label
32 v_add_i32 v0, vcc, 3.125, v0 label
/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s10 v_add_i32 v256, v0, v1 label
13 v_add_i32 v257, v0, v1 label
Dvop2.s99 v_add_i32 v0, vcc, 0.5, v0 label
103 v_add_i32 v0, vcc, 3.125, v0 label
267 v_add_i32 v1, vcc, v2, v3 label
271 v_add_i32 v1, s[0:1], v2, v3 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dlds_direct-err.s74 v_add_i32 v0, v0, lds_direct label
77 v_add_i32 lds_direct, v0, v0 label
Dout-of-range-registers.s22 v_add_i32 v256, v0, v1 label
28 v_add_i32 v257, v0, v1 label
Dvop3-gfx9.s694 v_add_i32 v1, v2, v3 label
699 v_add_i32 v1, v2, v3 clamp label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dadd_i64.ll7 ; SI: v_add_i32
57 ; SI: v_add_i32
59 ; SI: v_add_i32
Dmad_64_32.ll9 ; SI: v_add_i32
24 ; SI: v_add_i32
39 ; SI: v_add_i32
54 ; SI: v_add_i32
Dr600.add.ll80 ; FUNC-LABEL: {{^}}v_add_i32:
81 define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
117 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
Dadd.ll84 ; FUNC-LABEL: {{^}}v_add_i32:
89 define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
124 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
Dmove-addr64-rsrc-dead-subreg-writes.ll6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
Dearly-if-convert.ll407 ; GCN: v_add_i32
408 ; GCN: v_add_i32
432 ; GCN: v_add_i32
433 ; GCN: v_add_i32
Dsplit-scalar-i64-add.ll39 ; SI: v_add_i32
Dsaddo.ll140 ; GFX9-NEXT: v_add_i32 v1, s0, v1 clamp
218 ; GFX9-NEXT: v_add_i32 v3, v1, v2 clamp
468 ; GFX9-NEXT: v_add_i32 v5, v0, v2 clamp
470 ; GFX9-NEXT: v_add_i32 v2, v1, v3 clamp
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsaddsat.ll1028 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
1087 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1132 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
1193 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1235 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1272 ; GFX9-NEXT: v_add_i32 v0, v0, s0 clamp
1330 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
1331 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
1406 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1407 ; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
[all …]

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