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Searched refs:v_add_i32_e32 (Results 1 – 25 of 128) sorted by relevance

123456

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dsdiv.i64.ll20 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v2, v4
29 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v0, v8
45 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v13
46 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v15
51 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v13, v15
53 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v13, v16
56 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v15, v13
59 ; CHECK-NEXT: v_add_i32_e32 v14, vcc, v16, v14
61 ; CHECK-NEXT: v_add_i32_e32 v14, vcc, v14, v15
63 ; CHECK-NEXT: v_add_i32_e32 v15, vcc, v16, v15
[all …]
Dsrem.i64.ll20 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v2, v4
29 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v0, v7
45 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12
46 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v14
51 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v14
53 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v12, v15
56 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v14, v12
59 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v15, v13
61 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v13, v14
63 ; CHECK-NEXT: v_add_i32_e32 v14, vcc, v15, v14
[all …]
Dudiv.i64.ll35 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
39 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
44 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
48 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
50 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v14
52 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
53 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
54 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
56 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
[all …]
Durem.i64.ll35 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
39 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
44 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v11
46 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v13, v9
48 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
50 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v14
52 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
53 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
54 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
56 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
[all …]
Dsdiv.i32.ll13 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
14 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v3
24 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
27 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
33 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v4
47 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
48 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3
59 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3
60 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
63 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
[all …]
Dudiv.i32.ll18 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
21 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v2
27 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v2
43 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v4, v3
44 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
47 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
49 ; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
55 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2
76 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
79 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, 1, v0
[all …]
Dsrem.i32.ll13 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
14 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v3
24 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
43 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
44 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3
55 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
56 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4
59 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v4, v3
94 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
125 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v1
[all …]
Dmul.ll215 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s1, v0
255 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v4
256 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v0
296 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s7, v0
306 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s0, v2
308 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, s8, v1
309 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
310 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1
386 ; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v8
388 ; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v9
[all …]
Durem.i32.ll18 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
41 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v4, v3
42 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
45 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
72 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
95 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v1
96 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
99 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v1, v0
134 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
135 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-local-redundant-copies.ll10 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 12, v0
11 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 8, v0
12 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v0
33 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, 28, v1
34 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 24, v1
35 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 20, v1
36 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 16, v1
37 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 12, v1
38 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 8, v1
39 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v1
[all …]
Duaddsat.ll13 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
45 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
70 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
95 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
98 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
130 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
135 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
137 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
172 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
175 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
[all …]
Dload-local.128.ll25 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
137 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 5, v0
138 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
139 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 7, v0
140 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 6, v0
141 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 9, v0
142 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 8, v0
143 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, 11, v0
153 ; GFX6-NEXT: v_add_i32_e32 v9, vcc, 14, v0
154 ; GFX6-NEXT: v_add_i32_e32 v10, vcc, 3, v0
[all …]
Dsrem64.ll33 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
34 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
40 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
44 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
47 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
54 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
56 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
63 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
66 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
69 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
[all …]
Dload-local.96.ll25 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
117 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 5, v0
118 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
119 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 7, v0
120 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 6, v0
121 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 9, v0
122 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 8, v0
123 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, 11, v0
142 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 10, v0
143 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 3, v0
[all …]
Dudiv64.ll31 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
32 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
38 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
42 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
45 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
53 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
55 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
62 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
65 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
68 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
[all …]
Durem64.ll33 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
34 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
40 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
44 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
47 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
54 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
56 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
63 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
66 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
69 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
[all …]
Dsdiv64.ll38 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
39 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
45 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
49 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
52 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
60 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
62 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
69 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
72 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
75 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
[all …]
Dearly-if-convert-cost.ll55 ; GCN: v_add_i32_e32
56 ; GCN: v_add_i32_e32
57 ; GCN: v_add_i32_e32
86 ; GCN: v_add_i32_e32
87 ; GCN: v_add_i32_e32
88 ; GCN: v_add_i32_e32
89 ; GCN: v_add_i32_e32
Dsalu-to-valu.ll112 ; GCN-NOHSA: v_add_i32_e32
252 ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
311 ; GCN-NOHSA: v_add_i32_e32
312 ; GCN-NOHSA: v_add_i32_e32
313 ; GCN-NOHSA: v_add_i32_e32
314 ; GCN-NOHSA: v_add_i32_e32
315 ; GCN-NOHSA: v_add_i32_e32
316 ; GCN-NOHSA: v_add_i32_e32
317 ; GCN-NOHSA: v_add_i32_e32
373 ; GCN-NOHSA: v_add_i32_e32
[all …]
Dds-negative-offset-addressing-mode-loop.ll11 ; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
13 ; SI-DAG: v_add_i32_e32 [[VADDR8:v[0-9]+]], vcc, 8, [[VADDR]]
15 ; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]
17 ; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]]
19 ; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]]
Dllvm.mulo.ll17 ; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v7
19 ; SI-NEXT: v_add_i32_e32 v6, vcc, v1, v5
23 ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
69 ; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8
71 ; SI-NEXT: v_add_i32_e32 v9, vcc, v8, v5
77 ; SI-NEXT: v_add_i32_e32 v8, vcc, v8, v11
151 ; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v0
154 ; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4
157 ; SI-NEXT: v_add_i32_e32 v3, vcc, s5, v0
158 ; SI-NEXT: v_add_i32_e32 v0, vcc, s1, v1
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dudivrem.ll36 ; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
45 ; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]
49 ; SI-DAG: v_add_i32_e32 [[Remainder_A_Den:v[0-9]+]],
120 ; SI-DAG: v_add_i32_e32
129 ; SI-DAG: v_add_i32_e32
133 ; SI-DAG: v_add_i32_e32
143 ; SI-DAG: v_add_i32_e32
152 ; SI-DAG: v_add_i32_e32
156 ; SI-DAG: v_add_i32_e32
270 ; SI-DAG: v_add_i32_e32
[all …]
Dsalu-to-valu.ll112 ; GCN-NOHSA: v_add_i32_e32
249 ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
308 ; GCN-NOHSA: v_add_i32_e32
309 ; GCN-NOHSA: v_add_i32_e32
310 ; GCN-NOHSA: v_add_i32_e32
311 ; GCN-NOHSA: v_add_i32_e32
312 ; GCN-NOHSA: v_add_i32_e32
313 ; GCN-NOHSA: v_add_i32_e32
314 ; GCN-NOHSA: v_add_i32_e32
370 ; GCN-NOHSA: v_add_i32_e32
[all …]
Dds-negative-offset-addressing-mode-loop.ll11 ; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
13 ; SI-DAG: v_add_i32_e32 [[VADDR8:v[0-9]+]], vcc, 8, [[VADDR]]
15 ; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]
17 ; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]]
19 ; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]]
Dadd.ll8 ;SI: v_add_i32_e32 [[REG:v[0-9]+]], vcc, {{v[0-9]+, v[0-9]+}}
24 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
25 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
42 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
43 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
44 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
45 ;SI: v_add_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}

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