| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | add-sub-no-carry.s | 8 v_add_u32 v1, v2, v3 label
13 v_add_u32 v1, v2, s1 label
18 v_add_u32 v1, s1, v2 label
23 v_add_u32 v1, 4.0, v2 label
28 v_add_u32 v1, v2, 4.0 label
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| D | literals.s | 576 v_add_u32 v0, execz, v0 label
715 v_add_u32 v0, src_shared_base, v0 label
800 v_add_u32 v0, private_base, s0 label
805 v_add_u32 v0, scc, s0 label
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| D | vop2.s | 303 v_add_u32 v1, vcc, v2, v3 label
307 v_add_u32 v1, s[0:1], v2, v3 label
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| D | vop_sdwa.s | 1143 v_add_u32 v1, v[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
1148 v_add_u32 v1, s[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
1153 v_add_u32 v1, v3, v[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
1158 v_add_u32 v1, v3, s[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
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| D | vop3-gfx9.s | 625 v_add_u32 v84, v13, s31 clamp label
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| D | vop3.s | 304 v_add_u32 v84, vcc, v13, s31 clamp label
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| D | vop_dpp.s | 537 v_add_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
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| D | gfx10_unsupported.s | 89 v_add_u32 v0, execz, v0 label
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| D | gfx7_unsupported.s | 835 v_add_u32 v0, execz, v0 label
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| D | gfx8_asm_all.s | 38938 v_add_u32 v5, vcc, v1, v2 label
38941 v_add_u32 v255, vcc, v1, v2 label
38944 v_add_u32 v5, vcc, v255, v2 label
38947 v_add_u32 v5, vcc, s1, v2 label
38950 v_add_u32 v5, vcc, s101, v2 label
38953 v_add_u32 v5, vcc, flat_scratch_lo, v2 label
38956 v_add_u32 v5, vcc, flat_scratch_hi, v2 label
38959 v_add_u32 v5, vcc, vcc_lo, v2 label
38962 v_add_u32 v5, vcc, vcc_hi, v2 label
38965 v_add_u32 v5, vcc, tba_lo, v2 label
[all …]
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| D | gfx9_asm_all.s | 36758 v_add_u32 v5, v1, v2 label
36761 v_add_u32 v255, v1, v2 label
36764 v_add_u32 v5, v255, v2 label
36767 v_add_u32 v5, s1, v2 label
36770 v_add_u32 v5, s101, v2 label
36773 v_add_u32 v5, flat_scratch_lo, v2 label
36776 v_add_u32 v5, flat_scratch_hi, v2 label
36779 v_add_u32 v5, vcc_lo, v2 label
36782 v_add_u32 v5, vcc_hi, v2 label
36785 v_add_u32 v5, m0, v2 label
[all …]
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| /external/mesa3d/src/amd/compiler/tests/ |
| D | test_optimizer.cpp | 240 Builder::Result tmp = bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
241 writeout(0, bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp));
246 tmp = bld.vop2_e64(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
248 writeout(1, bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp));
253 tmp = bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
254 tmp = bld.vop2_e64(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp);
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| /external/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 283 v_add_u32 v1, vcc, v2, v3 label
287 v_add_u32 v1, s[0:1], v2, v3 label
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_optimizer.cpp | 539 case aco_opcode::v_add_u32: in can_swap_operands()
747 case aco_opcode::v_add_u32: in parse_base_offset()
1399 case aco_opcode::v_add_u32: in label_instruction()
2861 } else if (instr->opcode == aco_opcode::v_add_u32) { in combine_instruction()
2868 …else if (combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add3_u32, "012", 1… in combine_instruction()
2884 … combine_three_valu_op(ctx, instr, aco_opcode::v_add_u32, aco_opcode::v_add_lshl_u32, "120", 2); in combine_instruction()
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| D | aco_lower_to_hw_instr.cpp | 84 return aco_opcode::v_add_u32; in get_reduce_opcode()
145 case iadd32: return chip >= GFX9 ? aco_opcode::v_add_u32 : aco_opcode::v_add_co_u32; in get_reduce_opcode()
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| D | aco_instruction_selection.cpp | 1590 …OP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::… in visit_alu_instr()
11397 …Temp sgincl = bld.vop2_dpp(aco_opcode::v_add_u32, bld.def(v1), red_per_w, red_per_w, dpp_row_sr(1)… in ngg_gs_workgroup_reduce_and_scan()
11398 …sgincl = bld.vop2_dpp(aco_opcode::v_add_u32, bld.def(v1), sgincl, sgincl, dpp_row_sr(2), 0x1, 0xf,… in ngg_gs_workgroup_reduce_and_scan()
11399 …sgincl = bld.vop2_dpp(aco_opcode::v_add_u32, bld.def(v1), sgincl, sgincl, dpp_row_sr(4), 0x1, 0xf,… in ngg_gs_workgroup_reduce_and_scan()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 525 defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
1547 defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 508 defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
1471 defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_I32", "v_add_u32">;
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 1035 v_add_u32 v0, -1, 0 // src0 = 0xFFFFFFFF
1101 v_add_u32 v0, 1.0, 0 // src0 = 0x3F800000
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 3558 def : MnemonicAlias<"v_add_u32", "v_add_i32">;
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX8.rst | 885 …v_add_u32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:…
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| D | AMDGPUAsmGFX9.rst | 1072 …v_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
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| /external/mesa3d/docs/relnotes/ |
| D | 20.3.0.rst | 4140 - aco: disallow various v_add_u32 opts if modifiers are used
|