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Searched refs:v_and_b32 (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dfabs.f64.ll11 ; SI: v_and_b32
24 ; SI: v_and_b32
25 ; SI-NOT: v_and_b32
34 ; SI: v_and_b32
35 ; SI: v_and_b32
44 ; SI: v_and_b32
45 ; SI: v_and_b32
46 ; SI: v_and_b32
47 ; SI: v_and_b32
80 ; SI: v_and_b32
[all …]
Dfabs.ll14 ; GCN: v_and_b32
27 ; GCN: v_and_b32
39 ; GCN: v_and_b32
50 ; GCN: v_and_b32
51 ; GCN: v_and_b32
64 ; GCN: v_and_b32
65 ; GCN: v_and_b32
66 ; GCN: v_and_b32
67 ; GCN: v_and_b32
Dand-gcn.ll5 ; SI: v_and_b32
6 ; SI: v_and_b32
Dcopy-illegal-type.ll59 ; SI: v_and_b32
77 ; SI-DAG: v_and_b32
Dand.ll173 ; SI: v_and_b32
239 ; SI: v_and_b32
240 ; SI: v_and_b32
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfabs.f64.ll11 ; SI: v_and_b32
24 ; SI: v_and_b32
25 ; SI-NOT: v_and_b32
34 ; SI: v_and_b32
35 ; SI: v_and_b32
44 ; SI: v_and_b32
45 ; SI: v_and_b32
46 ; SI: v_and_b32
47 ; SI: v_and_b32
80 ; SI: v_and_b32
[all …]
Dnand.ll63 ; GCN: v_and_b32
74 ; GCN: v_and_b32
75 ; GCN: v_and_b32
Dlower-range-metadata-intrinsic-call.ll17 ; CHECK-NOT: v_and_b32
29 ; CHECK-NOT: v_and_b32
Dllvm.trunc.f16.ll35 ; SI-NOT: v_and_b32
40 ; VI-NOT: v_and_b32
Dllvm.sqrt.f16.ll35 ; SI-NOT: v_and_b32
40 ; VI-NOT: v_and_b32
Dllvm.rint.f16.ll36 ; SI-NOT: v_and_b32
41 ; VI-NOT: v_and_b32
Dandorn2.ll52 ; GCN: v_and_b32
65 ; GCN: v_and_b32
Ddagcombine-select.ll6 ; GCN-NOT: v_and_b32
19 ; GCN-NOT: v_and_b32
32 ; GCN-NOT: v_and_b32
47 ; GCN-NOT: v_and_b32
Dconstant-fold-mi-operands.ll127 ; GCN: v_and_b32
128 ; GCN-NOT: v_and_b32
Dllvm.fmuladd.f16.ll158 ; VI-FLUSH-NOT: v_and_b32
167 ; VI-DENORM-NOT: v_and_b32
/external/llvm-project/llvm/test/MC/AMDGPU/
Dexpressions.s110 v_and_b32 v0, i1+1, v0 label
113 v_and_b32 v0, 1+i1, v0 label
116 v_and_b32 v0, -i1+3, v0 label
119 v_and_b32 v0, -(i1+1), v0 label
156 v_and_b32 v0, i1+100, v0 label
159 v_and_b32 v0, -i1+102, v0 label
189 v_and_b32 v0, u+1, v0 label
Dliteral16-err.s27 v_and_b32 v1, 0x0000000100000000, v2 label
Dvop_dpp.s388 v_and_b32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
614 v_and_b32 v0, 42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
629 v_and_b32 v0, s42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
Dvop3-convert.s280 v_and_b32 v1, v2, v3 label
Dvop_sdwa.s80 v_and_b32 v0, v0, v0 dst_unused:UNUSED_PAD src1_sel:BYTE_2 label
112 v_and_b32 v0, sext(v0), sext(v0) dst_unused:UNUSED_PAD src1_sel:BYTE_2 label
384 v_and_b32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
/external/mesa3d/src/amd/compiler/tests/
Dtest_optimizer.cpp54 Temp abs_neg_a = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), neg_a);
59 Temp abs_a = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), inputs[0]);
100 writeout(0, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), inputs[0], subbrev));
105 writeout(1, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(42u), subbrev));
112 writeout(2, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), inputs[1], subbrev));
120 writeout(3, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), xor_a, subbrev));
126 writeout(4, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(inputs[0]), sub));
/external/llvm/test/MC/AMDGPU/
Dvop_sdwa.s81 v_and_b32 v0, v0, v0 dst_unused:UNUSED_PAD src1_sel:BYTE_2 label
113 v_and_b32 v0, sext(v0), sext(v0) dst_unused:UNUSED_PAD src1_sel:BYTE_2 label
357 v_and_b32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
Dvop2.s227 v_and_b32 v1, v2, v3 label
Dvop_dpp.s350 v_and_b32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp157 case iand32: return aco_opcode::v_and_b32; in get_reduce_opcode()
226 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], in emit_int64_dpp_op()
228 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], in emit_int64_dpp_op()
341 bld.vop2(aco_opcode::v_and_b32, dst[0], src0[0], src1[0]); in emit_int64_op()
342 bld.vop2(aco_opcode::v_and_b32, dst[1], src0[1], src1[1]); in emit_int64_op()
1044 bld.vop2(aco_opcode::v_and_b32, dst, Operand(~(0xffffu << offset)), def_op); in copy_constant()
1098 …bld.vop2(aco_opcode::v_and_b32, lo_half, Operand((1 << bits) - 1u), Operand(lo_reg, lo_half.regCla… in do_copy()
1256 bld.vop2(aco_opcode::v_and_b32, def_hi, Operand(~0xFFFFu), hi); in do_pack_2x16()
1265 bld.vop2(aco_opcode::v_and_b32, def_lo, Operand(0xFFFFu), lo); in do_pack_2x16()

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