| /external/llvm/test/CodeGen/AMDGPU/ |
| D | load-global-i32.ll | 170 ; GCN-DAG: v_ashrrev_i32
171 ; GCN-DAG: v_ashrrev_i32
201 ; GCN-DAG: v_ashrrev_i32
202 ; GCN-DAG: v_ashrrev_i32
203 ; GCN-DAG: v_ashrrev_i32
204 ; GCN-DAG: v_ashrrev_i32
248 ; GCN-DAG: v_ashrrev_i32
249 ; GCN-DAG: v_ashrrev_i32
250 ; GCN-DAG: v_ashrrev_i32
251 ; GCN-DAG: v_ashrrev_i32
[all …]
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| D | sdiv.ll | 42 ; SI: v_ashrrev_i32
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| D | kernel-args.ll | 522 ; SI: v_ashrrev_i32
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | load-global-i32.ll | 172 ; GCN-DAG: v_ashrrev_i32
173 ; GCN-DAG: v_ashrrev_i32
203 ; GCN-DAG: v_ashrrev_i32
204 ; GCN-DAG: v_ashrrev_i32
205 ; GCN-DAG: v_ashrrev_i32
206 ; GCN-DAG: v_ashrrev_i32
250 ; GCN-DAG: v_ashrrev_i32
251 ; GCN-DAG: v_ashrrev_i32
252 ; GCN-DAG: v_ashrrev_i32
253 ; GCN-DAG: v_ashrrev_i32
[all …]
|
| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | lds_direct-gfx10.s | 22 v_ashrrev_i32 v0, src_lds_direct, v0 label
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| D | lds_direct-err.s | 17 v_ashrrev_i32 v0, lds_direct, v0 label
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| D | vop3-convert.s | 267 v_ashrrev_i32 v1, v2, v3 label
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| D | vop_dpp.s | 444 v_ashrrev_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
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| D | vop_sdwa.s | 440 v_ashrrev_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
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| D | gfx7_asm_all.s | 35880 v_ashrrev_i32 v5, v1, v2 label
35883 v_ashrrev_i32 v255, v1, v2 label
35886 v_ashrrev_i32 v5, v255, v2 label
35889 v_ashrrev_i32 v5, s1, v2 label
35892 v_ashrrev_i32 v5, s103, v2 label
35895 v_ashrrev_i32 v5, flat_scratch_lo, v2 label
35898 v_ashrrev_i32 v5, flat_scratch_hi, v2 label
35901 v_ashrrev_i32 v5, vcc_lo, v2 label
35904 v_ashrrev_i32 v5, vcc_hi, v2 label
35907 v_ashrrev_i32 v5, tba_lo, v2 label
[all …]
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| D | gfx8_asm_all.s | 37702 v_ashrrev_i32 v5, v1, v2 label
37705 v_ashrrev_i32 v255, v1, v2 label
37708 v_ashrrev_i32 v5, v255, v2 label
37711 v_ashrrev_i32 v5, s1, v2 label
37714 v_ashrrev_i32 v5, s101, v2 label
37717 v_ashrrev_i32 v5, flat_scratch_lo, v2 label
37720 v_ashrrev_i32 v5, flat_scratch_hi, v2 label
37723 v_ashrrev_i32 v5, vcc_lo, v2 label
37726 v_ashrrev_i32 v5, vcc_hi, v2 label
37729 v_ashrrev_i32 v5, tba_lo, v2 label
[all …]
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| D | gfx9_asm_all.s | 32078 v_ashrrev_i32 v5, v1, v2 label
32081 v_ashrrev_i32 v255, v1, v2 label
32084 v_ashrrev_i32 v5, v255, v2 label
32087 v_ashrrev_i32 v5, s1, v2 label
32090 v_ashrrev_i32 v5, s101, v2 label
32093 v_ashrrev_i32 v5, flat_scratch_lo, v2 label
32096 v_ashrrev_i32 v5, flat_scratch_hi, v2 label
32099 v_ashrrev_i32 v5, vcc_lo, v2 label
32102 v_ashrrev_i32 v5, vcc_hi, v2 label
32105 v_ashrrev_i32 v5, m0, v2 label
[all …]
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| /external/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 214 v_ashrrev_i32 v1, v2, v3 label
|
| D | vop_dpp.s | 406 v_ashrrev_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
|
| D | vop_sdwa.s | 413 v_ashrrev_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 label
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 493 defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 481 defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
|
| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 606 Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), tmp); in convert_int()
1301 Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper); in visit_alu_instr()
1463 emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true); in visit_alu_instr()
2388 Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src); in visit_alu_instr()
4633 alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha); in adjust_vertex_fetch_alpha()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1537 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
|
| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 732 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
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| D | AMDGPUAsmGFX8.rst | 897 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`…
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| D | AMDGPUAsmGFX9.rst | 1084 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_3>`…
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| D | AMDGPUAsmGFX10.rst | 1437 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<am…
|