v_cndmask_b32_e32 (reference) in projects: external

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Searched refs:v_cndmask_b32_e32 (Results 1 – 25 of 117) sorted by relevance

12 3 4 5

/external/llvm/test/CodeGen/AMDGPU/
D	select-vectors.ll	`9 ; SI: v_cndmask_b32_e32 10 ; SI: v_cndmask_b32_e32 11 ; SI: v_cndmask_b32_e32 12 ; SI: v_cndmask_b32_e32 21 ; SI: v_cndmask_b32_e32 22 ; SI: v_cndmask_b32_e32 23 ; SI: v_cndmask_b32_e32 24 ; SI: v_cndmask_b32_e32 36 ; SI: v_cndmask_b32_e32 37 ; SI: v_cndmask_b32_e32 [all …]`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	select-vectors.ll	`29 ; GCN: v_cndmask_b32_e32 41 ; GCN: v_cndmask_b32_e32 42 ; GCN: v_cndmask_b32_e32 54 ; GCN: v_cndmask_b32_e32 55 ; GCN: v_cndmask_b32_e32 56 ; GCN: v_cndmask_b32_e32 57 ; GCN: v_cndmask_b32_e32 88 ; SI: v_cndmask_b32_e32 112 ; SI: v_cndmask_b32_e32 116 ; GFX89: v_cndmask_b32_e32 [all …]`
D	insert_vector_dynelt.ll	7 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] 9 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]] 11 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]] 13 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]] 65 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] 67 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC2]] 80 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_LAST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC1]] 82 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC2]] 84 ; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, [[CC3]] 86 ; GCN-DAG: v_cndmask_b32_e32 v[[ELT_FIRST0:[0-9]+]], 1.0, v{{[0-9]+}}, [[CC4]] [all …]
D	shift-i128.ll	`18 ; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc 20 ; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc 22 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 23 ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 43 ; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc 45 ; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc 47 ; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 48 ; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc 68 ; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc 70 ; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc [all …]`
D	vselect.ll	`16 ; SI: v_cndmask_b32_e32 18 ; SI: v_cndmask_b32_e32 36 ; SI: v_cndmask_b32_e32 38 ; SI: v_cndmask_b32_e32 62 ; SI: v_cndmask_b32_e32 63 ; SI: v_cndmask_b32_e32 64 ; SI: v_cndmask_b32_e32 65 ; SI: v_cndmask_b32_e32 83 ; SI: v_cndmask_b32_e32 84 ; SI: v_cndmask_b32_e32 [all …]`
D	early-if-convert-cost.ll	11 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc 12 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc 34 ; GCN: v_cndmask_b32_e32 35 ; GCN: v_cndmask_b32_e32 60 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc 61 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc 62 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc 92 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc 93 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc 94 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc [all …]
D	ssubsat.ll	59 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 83 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 97 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 140 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v5, v6, vcc 144 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc 152 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 203 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc 207 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc 214 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 221 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc [all …]
D	fmin_legacy.f64.ll	`22 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 23 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 40 ; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 41 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 74 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 75 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 92 ; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 93 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 126 ; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 127 ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc [all …]`
D	fmax_legacy.f64.ll	`24 ; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 25 ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 42 ; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 43 ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 76 ; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 77 ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 94 ; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 95 ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 128 ; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 129 ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc [all …]`
D	llvm.round.f64.ll	`22 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 35 ; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc 58 ; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc 95 ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc 98 ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc 99 ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc 104 ; SI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc 128 ; CI-NEXT: v_cndmask_b32_e32 v3, 0, v2, vcc 161 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 178 ; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc [all …]`
D	select-opt.ll	11 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 27 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 43 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 44 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 59 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 60 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 75 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 92 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 108 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc 109 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc [all …]
D	fdiv32-to-rcp-folding.ll	9 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc 29 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc 49 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc 70 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc 91 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc 93 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc 95 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc 97 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc 128 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc 130 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc [all …]
D	saddsat.ll	59 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 83 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 97 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 140 ; GFX8-NEXT: v_cndmask_b32_e32 v7, v5, v6, vcc 144 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc 152 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 202 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc 206 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc 213 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 220 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc [all …]
D	insert_vector_elt.ll	`294 ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 297 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 312 ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 315 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 335 ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 338 ; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 341 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 356 ; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 359 ; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 362 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc [all …]`
D	v_cndmask.ll	34 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, -1, v{{[0-9]+}}, vcc 57 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], [[CC]] 74 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VX]], [[CC]] 91 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], [[CC]] 108 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VX]], [[CC]] 159 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], vcc 177 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[Z]], vcc 196 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 2, [[Z]], vcc 216 ; SI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v[[Z_HI]], vcc 217 ; SI-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v[[Z_LO]], vcc [all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	extractelement.i128.ll	108 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc 109 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc 112 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc 113 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc 115 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 116 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 118 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc 119 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc 121 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc 122 ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc [all …]
D	extractelement.ll	`13 ; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc 18 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc 21 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 24 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 27 ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc 68 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc 71 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 74 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 77 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 80 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc [all …]`
D	udiv.i32.ll	24 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc 26 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 29 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc 52 ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc 54 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 57 ; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc 82 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 84 ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc 87 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 110 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc [all …]
D	fmin_legacy.ll	19 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 37 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 55 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 73 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 91 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 109 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 127 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 145 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 195 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 206 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc [all …]
D	urem.i32.ll	24 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 27 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 50 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 53 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 78 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 81 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 104 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 107 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 145 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 147 ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc [all …]
D	insertelement.ll	114 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc 117 ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc 120 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc 123 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc 126 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc 129 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc 132 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc 134 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc 158 ; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo 162 ; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo [all …]
D	floor.f64.ll	15 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 16 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc 58 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 59 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc 82 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 83 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc 125 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 126 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc 149 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 150 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc [all …]
D	fmax_legacy.ll	17 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 35 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 53 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 71 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 89 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 107 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 125 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 143 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 193 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 200 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc [all …]
D	sdiv.i32.ll	30 ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc 32 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc 35 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc 68 ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc 70 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 73 ; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc 106 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 108 ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc 111 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 144 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc [all …]
D	srem.i32.ll	30 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 33 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 64 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 67 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 100 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 103 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 134 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 137 ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 188 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc 190 ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc [all …]

12 3 4 5

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