v_cndmask_b32_e64 (reference) in projects: external

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Searched refs:v_cndmask_b32_e64 (Results 1 – 25 of 139) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
D	udivrem.ll	`34 ; SI: v_cndmask_b32_e64 38 ; SI: v_cndmask_b32_e64 42 ; SI-DAG: v_cndmask_b32_e64 43 ; SI-DAG: v_cndmask_b32_e64 47 ; SI-DAG: v_cndmask_b32_e64 48 ; SI-DAG: v_cndmask_b32_e64 51 ; SI-DAG: v_cndmask_b32_e64 52 ; SI-DAG: v_cndmask_b32_e64 118 ; SI-DAG: v_cndmask_b32_e64 122 ; SI-DAG: v_cndmask_b32_e64 [all …]`
D	setcc-opt.ll	8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 84 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 98 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 112 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 155 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 168 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc [all …]
D	ffloor.f64.ll	`18 ; SI: v_cndmask_b32_e64 19 ; SI: v_cndmask_b32_e64 33 ; SI: v_cndmask_b32_e64 34 ; SI: v_cndmask_b32_e64 49 ; SI: v_cndmask_b32_e64 50 ; SI: v_cndmask_b32_e64`
D	setcc.ll	101 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 133 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 146 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 160 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 174 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 188 ; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc 339 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, 341 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, 343 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, 360 ; SI-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, [all …]
D	llvm.amdgcn.class.ll	14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] 89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] 104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc [all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	urem.i64.ll	45 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 47 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 49 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 51 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 55 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 75 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] 77 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] 79 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] 81 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] 85 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] [all …]
D	srem.i64.ll	52 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 54 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 60 ; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc 62 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 65 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 82 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] 84 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] 90 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] 92 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] 95 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] [all …]
D	udiv.i64.ll	45 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc 47 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 49 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 51 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc 55 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc 75 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] 77 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] 79 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] 81 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] 85 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] [all …]
D	insertelement.i16.ll	548 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 572 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 596 ; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 713 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 741 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 769 ; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 801 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 828 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 856 ; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 885 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] [all …]
D	sdiv.i64.ll	52 ; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc 54 ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc 60 ; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc 62 ; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc 65 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc 82 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] 84 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] 90 ; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] 92 ; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] 95 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] [all …]
D	mul.ll	`305 ; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 335 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 387 ; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 389 ; GFX7-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 413 ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 415 ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 443 ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc 445 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc 468 ; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 485 ; GFX7-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc [all …]`
D	usubsat.ll	2495 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc 2496 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 2505 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc 2506 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 2515 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc 2516 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 2526 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc_lo 2527 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc_lo 2546 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc 2547 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc [all …]
D	insertelement.ll	796 ; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17] 798 ; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17] 800 ; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[4:5] 801 ; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[6:7] 802 ; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[8:9] 803 ; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v0, s[10:11] 804 ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v0, s[12:13] 805 ; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15] 806 ; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5] 807 ; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[6:7] [all …]
D	uaddsat.ll	2625 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc 2626 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc 2635 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc 2636 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc 2645 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc 2646 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc 2656 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo 2657 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo 2676 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc 2677 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc [all …]
D	extractelement.i128.ll	106 ; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, v4, s[4:5] 107 ; GFX9-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] 142 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[6:7] 143 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v13, s[6:7] 145 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v14, s[8:9] 146 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[8:9] 147 ; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v14, s[4:5] 148 ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[4:5] 165 ; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v10, s[4:5] 166 ; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v11, s[4:5] [all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
D	vop-err.s	114 v_cndmask_b32_e64 v0, s1, v2, vcc label 117 v_cndmask_b32_e64 v0, flat_scratch_lo, v2, vcc label 120 v_cndmask_b32_e64 v0, flat_scratch_hi, v2, vcc label 123 v_cndmask_b32_e64 v0, s1, v2, flat_scratch label 126 v_cndmask_b32_e64 v0, s0, v2, s[0:1] label 129 v_cndmask_b32_e64 v0, v2, s0, s[0:1] label 132 v_cndmask_b32_e64 v0, s0, s0, s[0:1] label 135 v_cndmask_b32_e64 v0, s1, v2, s[0:1] label 138 v_cndmask_b32_e64 v0, v2, s1, s[0:1] label 141 v_cndmask_b32_e64 v0, s1, s1, s[0:1] label [all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	shift-i128.ll	19 ; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5] 21 ; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5] 44 ; GCN-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] 46 ; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] 69 ; GCN-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] 71 ; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] 134 ; GCN-NEXT: v_cndmask_b32_e64 v2, 0, v1, s[4:5] 137 ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[4:5] 157 ; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v1, s[4:5] 175 ; GCN-NEXT: v_cndmask_b32_e64 v0, 33, v1, s[4:5] [all …]
D	ssubsat.ll	57 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 81 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 95 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 149 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[6:7] 212 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] 219 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] 289 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] 307 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] 335 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] 342 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] [all …]
D	llvm.round.f64.ll	25 ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] 27 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 29 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 96 ; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc 164 ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] 166 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 168 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 189 ; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] 191 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 193 ; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] [all …]
D	llvm.amdgcn.class.f16.ll	`10 ; GCN: v_cndmask_b32_e64 v[[R_I32:[0-9]+]] 31 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]] 53 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]] 75 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]] 96 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]] 112 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, [[CMP]] 129 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc 146 ; VI: v_cndmask_b32_e64 v[[VR_I32:[0-9]+]], 0, -1, vcc`
D	setcc-opt.ll	8 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 25 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 42 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 56 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 70 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 84 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 98 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 112 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 159 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc 172 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc [all …]
D	saddo.ll	30 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 50 ; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] 72 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 108 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 128 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 143 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 181 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 206 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 222 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc 259 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] [all …]
D	llvm.mulo.ll	`26 ; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 49 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 90 ; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 128 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc 162 ; SI-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc 163 ; SI-NEXT: v_cndmask_b32_e64 v0, v5, 0, vcc 191 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] 193 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] 245 ; SI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc 246 ; SI-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc [all …]`
D	llvm.amdgcn.class.ll	14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] 76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] 89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] 104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc 132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, s[{{[0-9]}}:{{[0-9]}}] 150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc [all …]
D	dagcombine-setcc-select.ll	`10 ; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1] 27 ; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1] 44 ; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1] 61 ; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]`

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