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Searched refs:v_lshlrev_b64 (Results 1 – 25 of 54) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Dexpressions-gfx10.s25 v_lshlrev_b64 v[5:6], i1+0xFFE, v[2:3] label
48 v_lshlrev_b64 v[5:6], u-1, v[2:3] label
Dvop3-literal.s314 v_lshlrev_b64 v[5:6], 0xaf123456, v[2:3] label
318 v_lshlrev_b64 v[5:6], v1, 0x3f717273 label
Dgfx10-constant-bus.s50 v_lshlrev_b64 v[5:6], 0x3f717273, 0x3f717273 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dshl-ext-reduce.ll89 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
97 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
132 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
140 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
168 ; GFX8-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]
183 ; GFX9-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]
243 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1]
258 ; GFX9-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2]
314 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
315 ; GFX8-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
[all …]
Dxnor.ll239 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
248 ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
257 ; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
283 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
292 ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
301 ; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]
Dshl.ll972 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
978 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
1027 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
1033 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
1095 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
1100 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]
1115 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1]
1120 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1]
1138 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
1139 ; GFX8-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbitreverse.ll297 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
307 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
317 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
407 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
416 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
425 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
534 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
549 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
551 ; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
566 ; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
[all …]
Dshl_add_ptr_global.ll6 ; GCN: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
23 ; GCN: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
Dshl_add_ptr_csub.ll4 ; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
Damdgpu-mul24-knownbits.ll12 ; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
Dllvm.amdgcn.s.barrier.ll59 ; VARIANT2-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
79 ; VARIANT3-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
Drotl.i64.ll22 ; VI-DAG: v_lshlrev_b64
Dllvm.amdgcn.qsad.pk.u16.u8.ll25 %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
Dllvm.amdgcn.mqsad.pk.u16.u8.ll25 %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
Dfshr.ll828 ; VI-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
831 ; VI-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
841 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
844 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
884 ; VI-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
887 ; VI-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
888 ; VI-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
894 ; VI-NEXT: v_lshlrev_b64 v[2:3], v7, v[2:3]
905 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
908 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
[all …]
Drotr.i64.ll24 ; VI-DAG: v_lshlrev_b64
Dbfe-combine.ll31 ; VI-SDWA: v_lshlrev_b64 v{{\[}}[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v{{\[}}[[ADDRBASE1]]:{{[^\]+}}]
Didiv-licm.ll251 ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
302 ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
356 ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
411 ; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3]
Dsext-in-reg.ll156 ; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
183 ; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
210 ; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
237 ; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
467 ; GFX89: v_lshlrev_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
497 ; GFX89: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}},
/external/llvm-project/clang/test/CodeGenOpenCL/
Dinline-asm-amdgcn.cl8 // CHECK: call i64 asm sideeffect "v_lshlrev_b64 v[15:16], 0, $0", "={v[15:16]},v"
9 __asm volatile("v_lshlrev_b64 v[15:16], 0, %0" : "={v[15:16]}"(v15_16) : "v"(arg0));
/external/llvm/test/CodeGen/AMDGPU/
Dshl.ll72 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
110 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
111 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
171 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
172 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
173 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
174 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
Drotl.i64.ll22 ; VI-DAG: v_lshlrev_b64
Drotr.i64.ll24 ; VI-DAG: v_lshlrev_b64
/external/llvm-project/llvm/test/Object/AMDGPU/
Dobjdump.s38 v_lshlrev_b64 v[10:11], 2, v[76:77]
/external/llvm/test/Object/AMDGPU/
Dobjdump.s34 v_lshlrev_b64 v[10:11], 2, v[76:77]

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