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Searched refs:v_mov_b32 (Results 1 – 25 of 69) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
89 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 64)
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
97 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 -16)
103 ; VI: v_mov_b32 {{v[0-9]+}}, 0x3c00
105 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 1.0 to i16))
111 ; VI: v_mov_b32 {{v[0-9]+}}, 0xbc00
113 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half -1.0 to i16))
119 ; VI: v_mov_b32 {{v[0-9]+}}, 0x3118
121 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(half 0xH3118)
[all …]
Dbitcast-vector-extract.ll10 ; GCN-NOT: v_mov_b32
12 ; GCN-NOT: v_mov_b32
26 ; GCN-NOT: v_mov_b32
28 ; GCN-NOT: v_mov_b32
42 ; GCN-NOT: v_mov_b32
44 ; GCN-NOT: v_mov_b32
58 ; GCN-NOT: v_mov_b32
60 ; GCN-NOT: v_mov_b32
Dinlineasm-16.ll15 ; GCN: v_mov_b32 v[[REG:[0-9]+]], -1
18 %v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
33 ; GCN: v_mov_b32 v[[REG:[0-9]+]], -1
36 %v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
Dmove-addr64-rsrc-dead-subreg-writes.ll11 ; GCN-NOT: v_mov_b32
14 ; GCN-NOT: v_mov_b32
16 ; GCN-NOT: v_mov_b32
Dllvm.amdgcn.mqsad.u32.u8.ll12 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
25 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
38 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
52 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
Datomic_optimizations_buffer.ll42 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
65 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
67 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
91 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
93 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
144 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
167 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
169 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
Datomic_optimizations_raw_buffer.ll41 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
59 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
61 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
112 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
130 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
132 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
Datomic_optimizations_struct_buffer.ll41 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
59 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
61 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
125 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
143 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
145 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
Datomic_optimizations_global_pointer.ll39 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
57 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
59 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
147 ; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
165 ; GFX89: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]]
167 ; GFX10: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[copy_value]]
Dinlineasm-packed.ll31 ; GCN: v_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
34 %val = call <2 x half> asm "v_mov_b32 $0, $1", "=v,r"(i32 %in) #0
Dindirect-addressing-si-pregfx9.ll15 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
33 %live.out.val = call i32 asm sideeffect "v_mov_b32 $0, 62", "=v"()
/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
Dvop_dpp.s16 v_mov_b32 v0, v0 quad_perm:[0,2,1,1] label
20 v_mov_b32 v0, v0 row_shl:1 label
24 v_mov_b32 v0, v0 row_shr:0xf label
28 v_mov_b32 v0, v0 row_ror:0xc label
32 v_mov_b32 v0, v0 wave_shl:1 label
36 v_mov_b32 v0, v0 wave_rol:1 label
40 v_mov_b32 v0, v0 wave_shr:1 label
44 v_mov_b32 v0, v0 wave_ror:1 label
48 v_mov_b32 v0, v0 row_mirror label
52 v_mov_b32 v0, v0 row_half_mirror label
[all …]
Ddata.s6 v_mov_b32 v7, s24
7 v_mov_b32 v8, s25
Dvop3-convert.s11 v_mov_b32 [v1], [v2] label
14 v_mov_b32 v0, 0.5 label
20 v_mov_b32 v1, ttmp8 label
25 v_mov_b32 v1, v2 label
/external/llvm/test/MC/AMDGPU/
Dvop_dpp.s12 v_mov_b32 v0, v0 quad_perm:[0,2,1,1] label
16 v_mov_b32 v0, v0 row_shl:1 label
20 v_mov_b32 v0, v0 row_shr:0xf label
24 v_mov_b32 v0, v0 row_ror:0xc label
28 v_mov_b32 v0, v0 wave_shl:1 label
32 v_mov_b32 v0, v0 wave_rol:1 label
36 v_mov_b32 v0, v0 wave_shr:1 label
40 v_mov_b32 v0, v0 wave_ror:1 label
44 v_mov_b32 v0, v0 row_mirror label
48 v_mov_b32 v0, v0 row_half_mirror label
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-inline-asm.ll27 …; CHECK: INLINEASM &"v_mov_b32 v0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit…
29 call void asm sideeffect "v_mov_b32 v0, 7", "~{v0}"(), !srcloc !0
56 …; CHECK: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 1835019 /…
63 call { i32, i32 } asm sideeffect "v_mov_b32 $0, 7; v_mov_b32 $1, 7", "=&v,=&v"(), !srcloc !0
75 ; CHECK: INLINEASM &"v_mov_b32 v1, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $vgpr1
81 %0 = tail call i32 asm "v_mov_b32 v1, 7", "={v1}"() nounwind
90 ; CHECK: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %1
96 %0 = tail call i32 asm "v_mov_b32 $0, 7", "=v"() nounwind
121 …; CHECK: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 1835018 /* regdef:VG…
128 %1 = call { float, float } asm "v_mov_b32 $0, 0; v_mov_b32 $1, 1", "=v,=v"()
[all …]
Dinline-asm.ll56 ; CHECK-NEXT: v_mov_b32 v0, s4
61 %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,s"(i32 %asm0) nounwind
74 ; CHECK-NEXT: v_mov_b32 v0, v0
79 %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind
/external/llvm-project/clang/test/CodeGenOpenCL/
Dinline-asm-amdgcn.cl40 // CHECK: call i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DA"(i64 8589934593)
41 __asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DA"(x));
47 // CHECK: call i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DB"(i64 8589934593)
48 __asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DB"(x));
/external/llvm/test/MC/AMDGPU/regression/
Dbug28538.s8 v_mov_b32 v0, v0 row_bcast:0 label
12 v_mov_b32 v0, v0 row_bcast:13 label
Dbug28413.s22 v_mov_b32 v0, 0.5 label
25 v_mov_b32 v0, 3.125 label
/external/llvm-project/llvm/test/MC/AMDGPU/regression/
Dbug28538.s8 v_mov_b32 v0, v0 row_bcast:0 label
12 v_mov_b32 v0, v0 row_bcast:13 label
/external/llvm/test/CodeGen/AMDGPU/
Dmove-addr64-rsrc-dead-subreg-writes.ll12 ; GCN-NOT: v_mov_b32
14 ; GCN-NOT: v_mov_b32
16 ; GCN-NOT: v_mov_b32
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp215 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
216 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], in emit_int64_dpp_op()
260 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
261 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[1], identity[1]); in emit_int64_dpp_op()
263 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], in emit_int64_dpp_op()
265 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[1], src0[1], in emit_int64_dpp_op()
284 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[1]); in emit_int64_dpp_op()
285 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[1], in emit_int64_dpp_op()
289 bld.vop1(aco_opcode::v_mov_b32, vtmp_def[0], identity[0]); in emit_int64_dpp_op()
290 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], in emit_int64_dpp_op()
[all …]
/external/llvm-project/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dinline-asm.ll20 ; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
22 %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
27 ; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
29 %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()

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