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Searched refs:v_pk_add_f16 (Results 1 – 25 of 31) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Dliteralv216.s11 v_pk_add_f16 v1, 0, v2 label
15 v_pk_add_f16 v1, 0.0, v2 label
19 v_pk_add_f16 v1, v2, 0 label
23 v_pk_add_f16 v1, v2, 0.0 label
27 v_pk_add_f16 v1, 1.0, v2 label
31 v_pk_add_f16 v1, -1.0, v2 label
35 v_pk_add_f16 v1, -0.5, v2 label
39 v_pk_add_f16 v1, 0.5, v2 label
43 v_pk_add_f16 v1, 2.0, v2 label
47 v_pk_add_f16 v1, -2.0, v2 label
[all …]
Dliteralv216-err.s4 v_pk_add_f16 v1, -17, v2 label
7 v_pk_add_f16 v1, 65, v2 label
10 v_pk_add_f16 v1, 64.0, v2 label
13 v_pk_add_f16 v1, -0.15915494, v2 label
16 v_pk_add_f16 v1, -0.0, v2 label
19 v_pk_add_f16 v1, -32768, v2 label
22 v_pk_add_f16 v1, 32767, v2 label
25 v_pk_add_f16 v1, 0xffffffffffff000f, v2 label
28 v_pk_add_f16 v1, 0x1000ffff, v2 label
Dvop3p-err.s63 v_pk_add_f16 v1, |v2|, v3 label
66 v_pk_add_f16 v1, abs(v2), v3 label
69 v_pk_add_f16 v1, v2, |v3| label
72 v_pk_add_f16 v1, v2, abs(v3) label
75 v_pk_add_f16 v1, -v2, v3 label
78 v_pk_add_f16 v1, v2, -v3 label
91 v_pk_add_f16 v255, s1, s2 label
Dvop3-literal.s70 v_pk_add_f16 v1, 25.0, v2 label
74 v_pk_add_f16 v1, 123456, v2 label
78 v_pk_add_f16 v1, -200, v2 label
82 v_pk_add_f16 v1, 25.0, 25.0 label
86 v_pk_add_f16 v1, 25.0, 25.1 label
342 v_pk_add_f16 v5, 0xaf123456, v2 label
346 v_pk_add_f16 v5, v1, 0x3f717273 label
350 v_pk_add_f16 v5, 0x3f717273, 0x3f717273 label
Dliterals.s601 v_pk_add_f16 v0, execz, v0 label
741 v_pk_add_f16 v0, src_shared_base, v0 label
859 v_pk_add_f16 v255, private_base, private_limit label
863 v_pk_add_f16 v255, vccz, execz label
Dvop3p.s158 v_pk_add_f16 v0, v1, v2 label
Dgfx10_err_pos.s842 v_pk_add_f16 v1, 25.0, 25.1 label
Dgfx8_unsupported.s1501 v_pk_add_f16 v0, execz, v0 label
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dliteralv216_gfx10.txt7 # GFX10: v_pk_add_f16 v1, 0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0x80,0x04,0x02,0x18]
10 # GFX10: v_pk_add_f16 v1, v2, 0 ; encoding: [0x01,0x00,0x0f,0xcc,0x02,0x01,0x01,0x18]
13 # GFX10: v_pk_add_f16 v1, 1.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf2,0x04,0x02,0x18]
16 # GFX10: v_pk_add_f16 v1, -1.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf3,0x04,0x02,0x18]
19 # GFX10: v_pk_add_f16 v1, -0.5, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf1,0x04,0x02,0x18]
22 # GFX10: v_pk_add_f16 v1, 0.5, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf0,0x04,0x02,0x18]
25 # GFX10: v_pk_add_f16 v1, 2.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf4,0x04,0x02,0x18]
28 # GFX10: v_pk_add_f16 v1, -2.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf5,0x04,0x02,0x18]
31 # GFX10: v_pk_add_f16 v1, 4.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf6,0x04,0x02,0x18]
34 # GFX10: v_pk_add_f16 v1, -4.0, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xf7,0x04,0x02,0x18]
[all …]
Dvop3-literal.txt24 # GFX10: v_pk_add_f16 v1, 0x4e40, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,…
27 # GFX10: v_pk_add_f16 v1, 0x1e240, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,…
30 # GFX10: v_pk_add_f16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x38,…
Dliteral_gfx9.txt48 # GFX9: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x8f,0xd3,0xeb,0x00,0x02,0x18]
129 # GFX9: v_pk_add_f16 v0, src_execz, v0 ; encoding: [0x00,0x00,0x8f,0xd3,0xfc,0x00,0x02,0x18]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfmuladd.v2f16.ll17 ; GFX9-FLUSH: v_pk_add_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
32 ; GFX9-DENORM-STRICT: v_pk_add_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
48 ; GFX9-FLUSH: v_pk_add_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
66 ; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
67 ; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
90 ; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
91 ; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
114 ; GFX9-FLUSH: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
115 ; GFX9-FLUSH: v_pk_add_f16 [[RESULT:v[0-9]+]], [[ADD0]], [[R2]]
117 ; GFX9-DENORM-STRICT: v_pk_add_f16 [[ADD0:v[0-9]+]], [[R1]], [[R1]]
[all …]
Dimmv216.ll121 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0 ; encoding
142 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x00,0x0f,0xc…
146 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x00,0x8f,0xd3…
167 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x00,0x0f,0x…
171 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x00,0x8f,0xd…
192 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1.0 op_sel_hi:[1,0] ; encoding
213 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -1.0 op_sel_hi:[1,0] ; encoding
235 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2.0 op_sel_hi:[1,0] ; encoding
256 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -2.0 op_sel_hi:[1,0] ; encoding
277 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 4.0 op_sel_hi:[1,0] ; encoding
[all …]
Dinlineasm-packed.ll49 ; GCN: v_pk_add_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
52 …%val = call <2 x half> asm "v_pk_add_f16 $0, $1, $2", "=v,r,v"(<2 x half> %in0, <2 x half> %in1) #0
Dstrict_fadd.f16.ll40 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
58 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
76 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v1
94 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v2
154 ; GFX9-NEXT: v_pk_add_f16 v0, s2, v0
Dreduction.ll5 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
23 ; GFX9-NEXT: v_pk_add_f16 [[ADD:v[0-9]+]], v0, v1 neg_lo:[0,1] neg_hi:[0,1]{{$}}
44 ; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]{{$}}
99 ; GFX9: v_pk_add_f16 [[ADD1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
100 ; GFX9-NEXT: v_pk_add_f16 [[ADD2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
101 ; GFX9-NEXT: v_pk_add_f16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}}
151 ; GFX9: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
152 ; GFX9-NEXT: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
153 ; GFX9-NEXT: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
154 ; GFX9: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
[all …]
Dfsub.f16.ll92 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] neg_lo:[0,1] neg_hi:[0,1]
128 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[B_V2_F16]], [[K]] neg_lo:[1,0] neg_hi:[1,0]
162 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], [[K]]{{$}}
Dclamp-modifier.ll192 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0] clamp{{$}}
207 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0] clamp{{$}}
222 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}}
239 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}}
258 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}}
277 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}}
313 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[A]], 1.0 op_sel_hi:[1,0]{{$}}
Dbuild-vector-packed-partial-undef.ll56 ; GFX9-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
249 ; GFX9-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
Dpacked-op-sel.ll568 ; GCN: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+$}}
582 ; GCN: v_pk_add_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} op_sel:[0,1] op_sel_hi:[1,0]{{$}}
627 ; GCN: v_pk_add_f16 [[FADD:v[0-9]+]]
662 ; GCN: v_pk_add_f16 [[FADD:v[0-9]+]]
Dfneg-fabs.f16.ll74 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[VAL]], [[K]]
Dllvm.fmuladd.f16.ll171 ; GFX10-FLUSH: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], [[MUL]], v[[C_V2_F16]]
/external/llvm-project/llvm/docs/
DAMDGPUInstructionSyntax.rst111 v_pk_add_f16
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td49 def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fadd>;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td56 def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, any_fadd>;

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