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Searched refs:v_readlane_b32 (Results 1 – 25 of 66) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpartial-sgpr-to-vgpr-spills.ll207 ; GCN-NEXT: v_readlane_b32 s8, v1, 56
208 ; GCN-NEXT: v_readlane_b32 s9, v1, 57
209 ; GCN-NEXT: v_readlane_b32 s10, v1, 58
210 ; GCN-NEXT: v_readlane_b32 s11, v1, 59
211 ; GCN-NEXT: v_readlane_b32 s12, v1, 60
212 ; GCN-NEXT: v_readlane_b32 s13, v1, 61
213 ; GCN-NEXT: v_readlane_b32 s14, v1, 62
214 ; GCN-NEXT: v_readlane_b32 s15, v1, 63
215 ; GCN-NEXT: v_readlane_b32 s16, v1, 48
216 ; GCN-NEXT: v_readlane_b32 s17, v1, 49
[all …]
Dspill-wide-sgpr.ll10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
Dindirect-call.ll259 ; GCN-NEXT: v_readlane_b32 s4, v43, 15
260 ; GCN-NEXT: v_readlane_b32 s5, v43, 16
261 ; GCN-NEXT: v_readlane_b32 s49, v43, 14
262 ; GCN-NEXT: v_readlane_b32 s48, v43, 13
263 ; GCN-NEXT: v_readlane_b32 s47, v43, 12
264 ; GCN-NEXT: v_readlane_b32 s46, v43, 11
265 ; GCN-NEXT: v_readlane_b32 s45, v43, 10
266 ; GCN-NEXT: v_readlane_b32 s44, v43, 9
267 ; GCN-NEXT: v_readlane_b32 s43, v43, 8
268 ; GCN-NEXT: v_readlane_b32 s42, v43, 7
[all …]
Dgfx-callable-argument-types.ll112 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0
113 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1
115 ; GFX9-NEXT: v_readlane_b32 s33, v40, 2
141 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0
142 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1
144 ; GFX10-NEXT: v_readlane_b32 s33, v40, 2
175 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0
176 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1
178 ; GFX9-NEXT: v_readlane_b32 s33, v40, 2
206 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0
[all …]
Dgfx-callable-preserved-registers.ll28 ; GFX9-NEXT: v_readlane_b32 s4, v40, 2
29 ; GFX9-NEXT: v_readlane_b32 s5, v40, 3
30 ; GFX9-NEXT: v_readlane_b32 s35, v40, 1
31 ; GFX9-NEXT: v_readlane_b32 s34, v40, 0
33 ; GFX9-NEXT: v_readlane_b32 s33, v40, 4
62 ; GFX10-NEXT: v_readlane_b32 s4, v40, 2
63 ; GFX10-NEXT: v_readlane_b32 s5, v40, 3
64 ; GFX10-NEXT: v_readlane_b32 s35, v40, 1
65 ; GFX10-NEXT: v_readlane_b32 s34, v40, 0
67 ; GFX10-NEXT: v_readlane_b32 s33, v40, 4
[all …]
Dcontrol-flow-fastregalloc.ll52 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
53 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
57 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
58 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
121 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
122 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
126 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
127 ; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
187 ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
188 ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
[all …]
Dcallee-frame-setup.ll105 ; MUBUF-DAG: v_readlane_b32 s5, [[CSR_VGPR]]
106 ; MUBUF-DAG: v_readlane_b32 s4, [[CSR_VGPR]]
107 ; FLATSCR-DAG: v_readlane_b32 s0, [[CSR_VGPR]]
108 ; FLATSCR-DAG: v_readlane_b32 s1, [[CSR_VGPR]]
112 ; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], 2
147 ; MUBUF-DAG: v_readlane_b32 s4, v40, 0
148 ; MUBUF-DAG: v_readlane_b32 s5, v40, 1
149 ; FLATSCR-DAG: v_readlane_b32 s0, v40, 0
150 ; FLATSCR-DAG: v_readlane_b32 s1, v40, 1
154 ; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], [[FP_SPILL_LANE]]
[all …]
Dspill_more_than_wavesize_csr_sgprs.ll7 ; CHECK-DAG: v_readlane_b32 s99, v1, 0
8 ; CHECK-DAG: v_readlane_b32 s98, v0, 63
28 ; CHECK-DAG: v_readlane_b32 s99, v2, 0
29 ; CHECK-DAG: v_readlane_b32 s98, v1, 63
Dcall-preserved-registers.ll38 ; MUBUF-DAG: v_readlane_b32 s4, v40, 2
39 ; MUBUF-DAG: v_readlane_b32 s5, v40, 3
40 ; FLATSCR-DAG: v_readlane_b32 s0, v40, 2
41 ; FLATSCR-DAG: v_readlane_b32 s1, v40, 3
42 ; GCN: v_readlane_b32 s35, v40, 1
43 ; GCN: v_readlane_b32 s34, v40, 0
45 ; GCN: v_readlane_b32 s33, v40, 4
67 ; GCN: v_readlane_b32 s33, v40, 4
233 ; GCN-NEXT: v_readlane_b32 s33, v0, 0
245 ; GCN-NEXT: v_readlane_b32 s34, v0, 0
[all …]
Dllvm.amdgcn.readlane.ll6 ; CHECK-NOT: v_readlane_b32
14 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
23 ; CHECK-NOT: v_readlane_b32
32 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]]
57 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32
Dcross-block-use-is-not-abi-copy.ll42 ; GCN-NEXT: v_readlane_b32 s4, v40, 0
43 ; GCN-NEXT: v_readlane_b32 s5, v40, 1
45 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
76 ; GCN-NEXT: v_readlane_b32 s4, v40, 0
77 ; GCN-NEXT: v_readlane_b32 s5, v40, 1
79 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
110 ; GCN-NEXT: v_readlane_b32 s4, v40, 0
111 ; GCN-NEXT: v_readlane_b32 s5, v40, 1
113 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
144 ; GCN-NEXT: v_readlane_b32 s4, v40, 0
[all …]
Dsi-spill-sgpr-stack.ll12 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 0
13 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 1
14 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 2
15 ; SGPR-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]], 3
Dcsr-gfx10.ll9 ; GFX10: v_readlane_b32 s105, v0, 1
10 ; GFX10: v_readlane_b32 s104, v0, 0
Dnested-calls.ll25 ; GCN: v_readlane_b32 s4, v40, 0
26 ; GCN: v_readlane_b32 s5, v40, 1
29 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
Dreserve-vgpr-for-sgpr-spill.ll14 ; GCN: v_readlane_b32 s30, v255, 0
15 ; GCN: v_readlane_b32 s31, v255, 1
16 ; GCN: v_readlane_b32 s33, v255, 2
60 ; GCN: v_readlane_b32 s30, v254, 0
61 ; GCN: v_readlane_b32 s31, v254, 1
62 ; GCN: v_readlane_b32 s33, v254, 2
103 ; GCN: v_readlane_b32 s4, v254, 2
Dbasic-branch.ll12 ; GCNNOOPT: v_readlane_b32
13 ; GCNNOOPT: v_readlane_b32
Datomic_optimizations_buffer.ll62 ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31
63 ; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
88 ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31
89 ; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
164 ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31
165 ; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
Datomic_optimizations_local_pointer.ll392 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
443 ; GFX9-NEXT: v_readlane_b32 s4, v2, 63
484 ; GFX1064-NEXT: v_readlane_b32 s4, v1, 31
487 ; GFX1064-NEXT: v_readlane_b32 s4, v1, 15
492 ; GFX1064-NEXT: v_readlane_b32 s5, v1, 31
497 ; GFX1064-NEXT: v_readlane_b32 s7, v1, 63
498 ; GFX1064-NEXT: v_readlane_b32 s6, v1, 47
550 ; GFX1032-NEXT: v_readlane_b32 s3, v1, 15
551 ; GFX1032-NEXT: v_readlane_b32 s4, v1, 31
631 ; GFX8-NEXT: v_readlane_b32 s4, v2, 63
[all …]
Dspill-m0.ll26 ; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]]
31 ; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 0
56 ; GCN-NOT: v_readlane_b32 m0
106 ; GCN-NOT: v_readlane_b32 m0
Datomic_optimizations_pixelshader.ll235 ; GFX8-NEXT: v_readlane_b32 s12, v2, 63
290 ; GFX9-NEXT: v_readlane_b32 s12, v2, 63
337 ; GFX1064-NEXT: v_readlane_b32 s12, v1, 31
340 ; GFX1064-NEXT: v_readlane_b32 s12, v1, 15
342 ; GFX1064-NEXT: v_readlane_b32 s13, v1, 31
347 ; GFX1064-NEXT: v_readlane_b32 s12, v1, 63
348 ; GFX1064-NEXT: v_readlane_b32 s14, v1, 47
399 ; GFX1032-NEXT: v_readlane_b32 s11, v1, 31
401 ; GFX1032-NEXT: v_readlane_b32 s10, v1, 15
Datomic_optimizations_raw_buffer.ll57 ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31
58 ; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
128 ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31
129 ; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63
Dmul24-pass-ordering.ll220 ; GFX9-NEXT: v_readlane_b32 s4, v43, 2
221 ; GFX9-NEXT: v_readlane_b32 s5, v43, 3
222 ; GFX9-NEXT: v_readlane_b32 s35, v43, 1
223 ; GFX9-NEXT: v_readlane_b32 s34, v43, 0
225 ; GFX9-NEXT: v_readlane_b32 s33, v43, 4
/external/llvm/test/CodeGen/AMDGPU/
Dbasic-branch.ll13 ; GCNNOOPT: v_readlane_b32
14 ; GCNNOOPT: v_readlane_b32
/external/llvm-project/llvm/test/MC/AMDGPU/
Dlds_direct-ci.s6 v_readlane_b32 s0, lds_direct, s0 label
Dlds_direct-gfx10.s7 v_readlane_b32 s0, lds_direct, s0 label

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