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Searched refs:v_writelane_b32 (Results 1 – 25 of 57) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpartial-sgpr-to-vgpr-spills.ll18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0
19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1
20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2
21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3
22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4
23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5
24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6
25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7
29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8
30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9
[all …]
Dspill-wide-sgpr.ll6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
[all …]
Dindirect-call.ll207 ; GCN-NEXT: v_writelane_b32 v43, s33, 17
213 ; GCN-NEXT: v_writelane_b32 v43, s34, 0
214 ; GCN-NEXT: v_writelane_b32 v43, s35, 1
215 ; GCN-NEXT: v_writelane_b32 v43, s36, 2
216 ; GCN-NEXT: v_writelane_b32 v43, s38, 3
217 ; GCN-NEXT: v_writelane_b32 v43, s39, 4
218 ; GCN-NEXT: v_writelane_b32 v43, s40, 5
219 ; GCN-NEXT: v_writelane_b32 v43, s41, 6
220 ; GCN-NEXT: v_writelane_b32 v43, s42, 7
221 ; GCN-NEXT: v_writelane_b32 v43, s43, 8
[all …]
Dgfx-callable-argument-types.ll101 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
102 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
109 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
130 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
137 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
139 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
163 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
164 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
170 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
194 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
[all …]
Dgfx-callable-preserved-registers.ll14 ; GFX9-NEXT: v_writelane_b32 v40, s33, 4
15 ; GFX9-NEXT: v_writelane_b32 v40, s34, 0
16 ; GFX9-NEXT: v_writelane_b32 v40, s35, 1
17 ; GFX9-NEXT: v_writelane_b32 v40, s30, 2
23 ; GFX9-NEXT: v_writelane_b32 v40, s31, 3
48 ; GFX10-NEXT: v_writelane_b32 v40, s33, 4
51 ; GFX10-NEXT: v_writelane_b32 v40, s34, 0
52 ; GFX10-NEXT: v_writelane_b32 v40, s35, 1
56 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2
57 ; GFX10-NEXT: v_writelane_b32 v40, s31, 3
[all …]
Dllvm.amdgcn.writelane.ll8 ; CIGFX9: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, m0
9 ; GFX10: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
18 ; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
28 ; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
43 ; CIGFX9: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], m0
44 ; GFX10: v_writelane_b32 v{{[0-9]+}}, m0, s{{[0-9]+}}
54 ; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
64 ; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
65 ; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
74 ; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
[all …]
Dcontrol-flow-fastregalloc.ll26 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
27 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
29 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
30 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
98 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
99 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
101 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
102 ; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
173 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
174 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
[all …]
Dspill_more_than_wavesize_csr_sgprs.ll4 ; CHECK-DAG: v_writelane_b32 v0, s98, 63
5 ; CHECK-DAG: v_writelane_b32 v1, s99, 0
25 ; CHECK-DAG: v_writelane_b32 v1, s98, 63
26 ; CHECK-DAG: v_writelane_b32 v2, s99, 0
Dcross-block-use-is-not-abi-copy.ll33 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
34 ; GCN-NEXT: v_writelane_b32 v40, s30, 0
40 ; GCN-NEXT: v_writelane_b32 v40, s31, 1
67 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
68 ; GCN-NEXT: v_writelane_b32 v40, s30, 0
74 ; GCN-NEXT: v_writelane_b32 v40, s31, 1
101 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
102 ; GCN-NEXT: v_writelane_b32 v40, s30, 0
108 ; GCN-NEXT: v_writelane_b32 v40, s31, 1
135 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
[all …]
Dcallee-frame-setup.ll92 ; GCN: v_writelane_b32 [[CSR_VGPR]], s33, 2
97 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30,
98 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31,
141 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s33, [[FP_SPILL_LANE:[0-9]+]]
143 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30, 0
144 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31, 1
176 ; GCN: v_writelane_b32 [[CSR_VGPR]], s
177 ; GCN: v_writelane_b32 [[CSR_VGPR]], s
217 ; GCN-NEXT: v_writelane_b32 v0, s42, 0
263 ; GCN-NEXT: v_writelane_b32 v1, s33, 63
[all …]
Dcall-preserved-registers.ll28 ; GCN: v_writelane_b32 v40, s33, 4
29 ; GCN: v_writelane_b32 v40, s34, 0
30 ; GCN: v_writelane_b32 v40, s35, 1
31 ; GCN: v_writelane_b32 v40, s30, 2
32 ; GCN: v_writelane_b32 v40, s31, 3
59 ; GCN: v_writelane_b32 v40, s33, 4
229 ; GCN: v_writelane_b32 v0, s33, 0
241 ; GCN: v_writelane_b32 v0, s34, 0
278 ; GCN: v_writelane_b32 v40, s40
310 ; GCN: v_writelane_b32 v41, s40
Dcsr-gfx10.ll5 ; GFX10: v_writelane_b32 v0, s104, 0
6 ; GFX10-DAG: v_writelane_b32 v0, s105, 1
Dnested-calls.ll17 ; GCN-DAG: v_writelane_b32 v40, s33, 2
20 ; GCN-DAG: v_writelane_b32 v40, s30, 0
21 ; GCN-DAG: v_writelane_b32 v40, s31, 1
Dreserve-vgpr-for-sgpr-spill.ll10 ; GCN: v_writelane_b32 v255, s33, 2
11 ; GCN: v_writelane_b32 v255, s30, 0
12 ; GCN: v_writelane_b32 v255, s31, 1
56 ; GCN: v_writelane_b32 v254, s33, 2
57 ; GCN: v_writelane_b32 v254, s30, 0
58 ; GCN: v_writelane_b32 v254, s31, 1
102 ; GCN: v_writelane_b32 v254, s4, 2
Dbasic-branch.ll8 ; GCNNOOPT: v_writelane_b32
9 ; GCNNOOPT: v_writelane_b32
Dmul24-pass-ordering.ll192 ; GFX9-NEXT: v_writelane_b32 v43, s33, 4
195 ; GFX9-NEXT: v_writelane_b32 v43, s34, 0
199 ; GFX9-NEXT: v_writelane_b32 v43, s35, 1
207 ; GFX9-NEXT: v_writelane_b32 v43, s30, 2
209 ; GFX9-NEXT: v_writelane_b32 v43, s31, 3
Dcall-graph-register-usage.ll16 ; GCN: v_writelane_b32 v40, s33, 2
17 ; GCN: v_writelane_b32 v40, s30, 0
18 ; GCN: v_writelane_b32 v40, s31, 1
Dspill-csr-frame-ptr-reg-copy.ll7 ; GCN: v_writelane_b32 v40, s33, 2
Dsibling-call.ll102 ; GCN-NOT: v_writelane_b32 v{{[0-9]+}}, s32
207 ; GCN-DAG: v_writelane_b32 v42, s34, 0
208 ; GCN-DAG: v_writelane_b32 v42, s35, 1
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.writelane.ll11 ; GFX7-NEXT: v_writelane_b32 v0, s2, m0
18 ; GFX8-NEXT: v_writelane_b32 v0, s2, m0
24 ; GFX10-NEXT: v_writelane_b32 v0, s2, s3
36 ; GFX7-NEXT: v_writelane_b32 v0, s2, m0
43 ; GFX8-NEXT: v_writelane_b32 v0, s2, m0
49 ; GFX10-NEXT: v_writelane_b32 v0, s2, s3
62 ; GFX7-NEXT: v_writelane_b32 v0, s0, m0
69 ; GFX8-NEXT: v_writelane_b32 v0, s0, m0
75 ; GFX10-NEXT: v_writelane_b32 v0, s0, s2
86 ; GFX7-NEXT: v_writelane_b32 v0, 42, s2
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dbasic-branch.ll7 ; GCNNOOPT: v_writelane_b32
8 ; GCNNOOPT: v_writelane_b32
9 ; GCNNOOPT: v_writelane_b32
/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop2.s139 v_writelane_b32 v1, s2, 4 label
143 v_writelane_b32 v2, 1, s4 label
147 v_writelane_b32 v255, 0xaf123456, 2 label
Dlds_direct-ci.s9 v_writelane_b32 v0, lds_direct, s0 label
Dlds_direct-gfx10.s10 v_writelane_b32 v0, lds_direct, s0 label
Dlds_direct-err.s60 v_writelane_b32 v0, lds_direct, s0 label

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