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Searched refs:vacge (Results 1 – 25 of 39) sorted by relevance

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/external/capstone/suite/MC/ARM/
Dneon-cmp-encoding.s.cs24 0xb1,0x0e,0x40,0xf3 = vacge.f32 d16, d16, d17
25 0xf2,0x0e,0x40,0xf3 = vacge.f32 q8, q8, q9
85 0xf6,0x2e,0x48,0xf3 = vacge.f32 q9, q12, q11
86 0x1b,0x9e,0x0c,0xf3 = vacge.f32 d9, d12, d11
87 0xf6,0x6e,0x48,0xf3 = vacge.f32 q11, q12, q11
88 0x1b,0xbe,0x0c,0xf3 = vacge.f32 d11, d12, d11
Dneon-bitwise-encoding.s.cs123 0x3e,0x5e,0x05,0xf3 = vacge.f32 d5, d5, d30
124 0x56,0xae,0x0a,0xf3 = vacge.f32 q5, q5, q3
/external/llvm-project/llvm/test/MC/ARM/
Dneon-cmp-encoding.s35 vacge.f32 d16, d16, d17
36 vacge.f32 q8, q8, q9
52 @ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3]
53 @ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3]
194 @ CHECK: vacge.f32 q9, q12, q11 @ encoding: [0xf6,0x2e,0x48,0xf3]
195 @ CHECK: vacge.f32 d9, d12, d11 @ encoding: [0x1b,0x9e,0x0c,0xf3]
196 @ CHECK: vacge.f32 q11, q12, q11 @ encoding: [0xf6,0x6e,0x48,0xf3]
197 @ CHECK: vacge.f32 d11, d12, d11 @ encoding: [0x1b,0xbe,0x0c,0xf3]
Dfullfp16-neon.s144 vacge.f16 d0, d1, d2
145 vacge.f16 q0, q1, q2
146 @ ARM: vacge.f16 d0, d1, d2 @ encoding: [0x12,0x0e,0x11,0xf3]
147 @ ARM: vacge.f16 q0, q1, q2 @ encoding: [0x54,0x0e,0x12,0xf3]
148 @ THUMB: vacge.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0e]
149 @ THUMB: vacge.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0e]
160 @ ARM: vacge.f16 d0, d2, d1 @ encoding: [0x11,0x0e,0x12,0xf3]
161 @ ARM: vacge.f16 q0, q2, q1 @ encoding: [0x52,0x0e,0x14,0xf3]
162 @ THUMB: vacge.f16 d0, d2, d1 @ encoding: [0x12,0xff,0x11,0x0e]
163 @ THUMB: vacge.f16 q0, q2, q1 @ encoding: [0x14,0xff,0x52,0x0e]
Dneon-bitwise-encoding.s335 vacge.f32 d5, d30
336 vacge.f32 q5, q3
Dfullfp16-neon-neg.s106 vacge.f16 d0, d1, d2
107 vacge.f16 q0, q1, q2
/external/llvm/test/MC/ARM/
Dneon-cmp-encoding.s35 vacge.f32 d16, d16, d17
36 vacge.f32 q8, q8, q9
52 @ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3]
53 @ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3]
194 @ CHECK: vacge.f32 q9, q12, q11 @ encoding: [0xf6,0x2e,0x48,0xf3]
195 @ CHECK: vacge.f32 d9, d12, d11 @ encoding: [0x1b,0x9e,0x0c,0xf3]
196 @ CHECK: vacge.f32 q11, q12, q11 @ encoding: [0xf6,0x6e,0x48,0xf3]
197 @ CHECK: vacge.f32 d11, d12, d11 @ encoding: [0x1b,0xbe,0x0c,0xf3]
Dfullfp16-neon.s144 vacge.f16 d0, d1, d2
145 vacge.f16 q0, q1, q2
146 @ ARM: vacge.f16 d0, d1, d2 @ encoding: [0x12,0x0e,0x11,0xf3]
147 @ ARM: vacge.f16 q0, q1, q2 @ encoding: [0x54,0x0e,0x12,0xf3]
148 @ THUMB: vacge.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0e]
149 @ THUMB: vacge.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0e]
160 @ ARM: vacge.f16 d0, d2, d1 @ encoding: [0x11,0x0e,0x12,0xf3]
161 @ ARM: vacge.f16 q0, q2, q1 @ encoding: [0x52,0x0e,0x14,0xf3]
162 @ THUMB: vacge.f16 d0, d2, d1 @ encoding: [0x12,0xff,0x11,0x0e]
163 @ THUMB: vacge.f16 q0, q2, q1 @ encoding: [0x14,0xff,0x52,0x0e]
Dfullfp16-neon-neg.s106 vacge.f16 d0, d1, d2
107 vacge.f16 q0, q1, q2
Dneon-bitwise-encoding.s328 vacge.f32 d5, d30
329 vacge.f32 q5, q3
/external/llvm/test/CodeGen/ARM/
Dvcge.ll145 ;CHECK: vacge.f32
148 %tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
154 ;CHECK: vacge.f32
157 %tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
161 declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
162 declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvcge.ll226 ; CHECK-NEXT: vacge.f32 d16, d17, d16
231 %tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
240 ; CHECK-NEXT: vacge.f32 q8, q9, q8
246 %tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
250 declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
251 declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
Darmv8.2a-fp16-vector-intrinsics.ll531 ; CHECK: vacge.f16 d0, d0, d1
534 %vcage_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
540 ; CHECK: vacge.f16 q0, q0, q1
543 %vcageq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
567 ; CHECK: vacge.f16 d0, d1, d0
570 %vcale_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
576 ; CHECK: vacge.f16 q0, q1, q0
579 %vcaleq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
1299 declare <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half>, <4 x half>)
1300 declare <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half>, <8 x half>)
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm.txt94 # CHECK: vacge.f16 d0, d1, d2
95 # CHECK: vacge.f16 q0, q1, q2
Dfullfp16-neon-thumb.txt94 # CHECK: vacge.f16 d0, d1, d2
95 # CHECK: vacge.f16 q0, q1, q2
Dneon.txt362 # CHECK: vacge.f32 d16, d16, d17
363 # CHECK: vacge.f32 q8, q8, q9
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt94 # CHECK: vacge.f16 d0, d1, d2
95 # CHECK: vacge.f16 q0, q1, q2
Dfullfp16-neon-arm.txt94 # CHECK: vacge.f16 d0, d1, d2
95 # CHECK: vacge.f16 q0, q1, q2
Dneon.txt371 # CHECK: vacge.f32 d16, d16, d17
372 # CHECK: vacge.f32 q8, q8, q9
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-neon-instructions.s180 vacge.f32 d16, d16, d17
181 vacge.f32 q8, q8, q9
1296 # CHECK-NEXT: 1 5 0.50 vacge.f32 d16, d16, d17
1297 # CHECK-NEXT: 1 5 0.50 vacge.f32 q8, q8, q9
2419 # CHECK-NEXT: - - - - - - 0.50 0.50 vacge.f32 d16, d16, d17
2420 # CHECK-NEXT: - - - - - - 0.50 0.50 vacge.f32 q8, q8, q9
/external/vixl/src/aarch32/
Dassembler-aarch32.h3834 void vacge(
3836 void vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacge() function
3837 vacge(al, dt, rd, rn, rm); in vacge()
3840 void vacge(
3842 void vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vacge() function
3843 vacge(al, dt, rd, rn, rm); in vacge()
Ddisasm-aarch32.h1472 void vacge(
1475 void vacge(
/external/llvm-project/clang/include/clang/Basic/
Darm_neon.td358 let InstName = "vacge" in {
1652 let InstName = "vacge" in {
/external/clang/include/clang/Basic/
Darm_neon.td558 let InstName = "vacge" in {
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9919 "bav\004vabd\005vabdl\004vabs\005vacge\005vacgt\005vacle\005vaclt\004vad"
11665 …{ 1993 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { M…
11666 …{ 1993 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { M…
11667 …{ 1993 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasF…
11668 …{ 1993 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasF…
11669 …{ 1993 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { M…
11670 …{ 1993 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { M…
11671 …{ 1993 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasF…
11672 …{ 1993 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasF…

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