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Searched refs:vaddhn (Results 1 – 25 of 31) sorted by relevance

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/external/llvm-project/llvm/test/MC/ARM/
Dneont2-add-encoding.s127 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04]
128 vaddhn.i16 d16, q8, q9
129 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xef,0xa2,0x04]
130 vaddhn.i32 d16, q8, q9
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
Dneon-add-encoding.s223 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2]
224 vaddhn.i16 d16, q8, q9
225 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2]
226 vaddhn.i32 d16, q8, q9
227 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
228 vaddhn.i64 d16, q8, q9
/external/llvm/test/MC/ARM/
Dneont2-add-encoding.s127 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04]
128 vaddhn.i16 d16, q8, q9
129 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xef,0xa2,0x04]
130 vaddhn.i32 d16, q8, q9
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
Dneon-add-encoding.s223 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2]
224 vaddhn.i16 d16, q8, q9
225 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2]
226 vaddhn.i32 d16, q8, q9
227 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
228 vaddhn.i64 d16, q8, q9
/external/capstone/suite/MC/ARM/
Dneont2-add-encoding.s.cs60 0xc0,0xef,0xa2,0x04 = vaddhn.i16 d16, q8, q9
61 0xd0,0xef,0xa2,0x04 = vaddhn.i32 d16, q8, q9
62 0xe0,0xef,0xa2,0x04 = vaddhn.i64 d16, q8, q9
Dneon-add-encoding.s.cs100 0xa2,0x04,0xc0,0xf2 = vaddhn.i16 d16, q8, q9
101 0xa2,0x04,0xd0,0xf2 = vaddhn.i32 d16, q8, q9
102 0xa2,0x04,0xe0,0xf2 = vaddhn.i64 d16, q8, q9
/external/arm-neon-tests/
Dref_vaddhn.c45 #define INSN_NAME vaddhn
DMakefile.gcc56 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
DMakefile50 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvadd.ll126 ; CHECK: vaddhn.i16
135 ; CHECK: vaddhn.i32
144 ; CHECK: vaddhn.i64
/external/llvm/test/CodeGen/ARM/
Dvadd.ll126 ; CHECK: vaddhn.i16
135 ; CHECK: vaddhn.i32
144 ; CHECK: vaddhn.i64
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-neon-3vdiff.ll549 %vaddhn.i = add <8 x i16> %a, %b
550 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
559 %vaddhn.i = add <4 x i32> %a, %b
560 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
569 %vaddhn.i = add <2 x i64> %a, %b
570 %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>
579 %vaddhn.i = add <8 x i16> %a, %b
580 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
589 %vaddhn.i = add <4 x i32> %a, %b
590 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-3vdiff.ll549 %vaddhn.i = add <8 x i16> %a, %b
550 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
559 %vaddhn.i = add <4 x i32> %a, %b
560 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
569 %vaddhn.i = add <2 x i64> %a, %b
570 %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>
579 %vaddhn.i = add <8 x i16> %a, %b
580 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
589 %vaddhn.i = add <4 x i32> %a, %b
590 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
[all …]
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-neon-instructions.s115 vaddhn.i16 d16, q8, q9
116 vaddhn.i32 d16, q8, q9
117 vaddhn.i64 d16, q8, q9
1231 # CHECK-NEXT: 1 3 0.50 vaddhn.i16 d16, q8, q9
1232 # CHECK-NEXT: 1 3 0.50 vaddhn.i32 d16, q8, q9
1233 # CHECK-NEXT: 1 3 0.50 vaddhn.i64 d16, q8, q9
2354 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i16 d16, q8, q9
2355 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i32 d16, q8, q9
2356 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i64 d16, q8, q9
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt236 # CHECK: vaddhn.i16 d16, q8, q9
238 # CHECK: vaddhn.i32 d16, q8, q9
240 # CHECK: vaddhn.i64 d16, q8, q9
Dneon.txt239 # CHECK: vaddhn.i16 d16, q8, q9
241 # CHECK: vaddhn.i32 d16, q8, q9
243 # CHECK: vaddhn.i64 d16, q8, q9
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dneont2.txt236 # CHECK: vaddhn.i16 d16, q8, q9
238 # CHECK: vaddhn.i32 d16, q8, q9
240 # CHECK: vaddhn.i64 d16, q8, q9
Dneon.txt239 # CHECK: vaddhn.i16 d16, q8, q9
241 # CHECK: vaddhn.i32 d16, q8, q9
243 # CHECK: vaddhn.i64 d16, q8, q9
/external/clang/include/clang/Basic/
Darm_neon.td428 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
514 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
/external/llvm-project/clang/include/clang/Basic/
Darm_neon.td135 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
314 def VADDHN : IInst<"vaddhn", "<QQ", "silUsUiUl">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h3900 void vaddhn(
3902 void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vaddhn() function
3903 vaddhn(al, dt, rd, rn, rm); in vaddhn()
Ddisasm-aarch32.h1505 void vaddhn(
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc1393 { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */
1396 { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */
1399 { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc1393 { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */
1396 { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */
1399 { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9920 "c\005vadci\004vadd\006vaddhn\005vaddl\006vaddlv\007vaddlva\005vaddv\006"
11739 …{ 2033 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON,…
11740 …{ 2033 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON…
11741 …{ 2033 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON…

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