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Searched refs:vcls (Results 1 – 25 of 43) sorted by relevance

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/external/llvm-project/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s19 @ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3]
20 vcls.s8 d16, d16
21 @ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3]
22 vcls.s16 d16, d16
23 @ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3]
24 vcls.s32 d16, d16
25 @ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3]
26 vcls.s8 q8, q8
27 @ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3]
28 vcls.s16 q8, q8
[all …]
Dneont2-bitcount-encoding.s25 vcls.s8 d16, d16
26 vcls.s16 d16, d16
27 vcls.s32 d16, d16
28 vcls.s8 q8, q8
29 vcls.s16 q8, q8
30 vcls.s32 q8, q8
32 @ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04]
[all …]
Dmve-integer.s225 # CHECK: vcls.s8 q2, q1 @ encoding: [0xb0,0xff,0x42,0x44]
226 vcls.s8 q2, q1
228 # CHECK: vcls.s16 q0, q4 @ encoding: [0xb4,0xff,0x48,0x04]
229 vcls.s16 q0, q4
231 # CHECK: vcls.s32 q0, q0 @ encoding: [0xb8,0xff,0x40,0x04]
232 vcls.s32 q0, q0
/external/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s19 @ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3]
20 vcls.s8 d16, d16
21 @ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3]
22 vcls.s16 d16, d16
23 @ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3]
24 vcls.s32 d16, d16
25 @ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3]
26 vcls.s8 q8, q8
27 @ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3]
28 vcls.s16 q8, q8
[all …]
Dneont2-bitcount-encoding.s25 vcls.s8 d16, d16
26 vcls.s16 d16, d16
27 vcls.s32 d16, d16
28 vcls.s8 q8, q8
29 vcls.s16 q8, q8
30 vcls.s32 q8, q8
32 @ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04]
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvcls.ll7 ; CHECK-NEXT: vcls.s8 q0, q0
10 %0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a)
17 ; CHECK-NEXT: vcls.s16 q0, q0
20 %0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a)
27 ; CHECK-NEXT: vcls.s32 q0, q0
30 %0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a)
34 declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>)
35 declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>)
36 declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)
/external/capstone/suite/MC/ARM/
Dneon-bitcount-encoding.s.cs10 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16
11 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16
12 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16
13 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8
14 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8
15 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8
Dneont2-bitcount-encoding.s.cs10 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16
11 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16
12 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16
13 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8
14 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8
15 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8
/external/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
159 ;CHECK: vcls.s8
161 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
167 ;CHECK: vcls.s16
169 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
175 ;CHECK: vcls.s32
177 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
183 ;CHECK: vcls.s8
185 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
191 ;CHECK: vcls.s16
[all …]
Dpopcnt.ll155 ;CHECK: vcls.s8
157 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
163 ;CHECK: vcls.s16
165 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
171 ;CHECK: vcls.s32
173 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
179 ;CHECK: vcls.s8
181 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
187 ;CHECK: vcls.s16
189 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
159 ;CHECK: vcls.s8
161 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
167 ;CHECK: vcls.s16
169 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
175 ;CHECK: vcls.s32
177 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
183 ;CHECK: vcls.s8
185 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
191 ;CHECK: vcls.s16
[all …]
Dpopcnt.ll213 ; CHECK-NEXT: vcls.s8 d16, d16
217 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
225 ; CHECK-NEXT: vcls.s16 d16, d16
229 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
237 ; CHECK-NEXT: vcls.s32 d16, d16
241 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
249 ; CHECK-NEXT: vcls.s8 q8, q8
254 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
262 ; CHECK-NEXT: vcls.s16 q8, q8
267 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dremat-vctp.ll18 ; CHECK-NEXT: vcls.s32 q3, q5
60 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)
120 ; CHECK-NEXT: vcls.s32 q3, q5
168 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)
205 declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)
/external/arm-neon-tests/
Dref_vcls.c34 #define INSN_NAME vcls
DMakefile.gcc59 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-integer.txt307 # CHECK: vcls.s8 q2, q1 @ encoding: [0xb0,0xff,0x42,0x44]
311 # CHECK: vcls.s16 q0, q4 @ encoding: [0xb4,0xff,0x48,0x04]
315 # CHECK: vcls.s32 q0, q0 @ encoding: [0xb8,0xff,0x40,0x04]
Dneont2.txt265 # CHECK: vcls.s8 d16, d16
267 # CHECK: vcls.s16 d16, d16
269 # CHECK: vcls.s32 d16, d16
271 # CHECK: vcls.s8 q8, q8
273 # CHECK: vcls.s16 q8, q8
275 # CHECK: vcls.s32 q8, q8
Dneon.txt269 # CHECK: vcls.s8 d16, d16
271 # CHECK: vcls.s16 d16, d16
273 # CHECK: vcls.s32 d16, d16
275 # CHECK: vcls.s8 q8, q8
277 # CHECK: vcls.s16 q8, q8
279 # CHECK: vcls.s32 q8, q8
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-neon-instructions.s129 vcls.s8 d16, d16
130 vcls.s16 d16, d16
131 vcls.s32 d16, d16
132 vcls.s8 q8, q8
133 vcls.s16 q8, q8
134 vcls.s32 q8, q8
1245 # CHECK-NEXT: 1 3 0.50 vcls.s8 d16, d16
1246 # CHECK-NEXT: 1 3 0.50 vcls.s16 d16, d16
1247 # CHECK-NEXT: 1 3 0.50 vcls.s32 d16, d16
1248 # CHECK-NEXT: 1 3 0.50 vcls.s8 q8, q8
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt265 # CHECK: vcls.s8 d16, d16
267 # CHECK: vcls.s16 d16, d16
269 # CHECK: vcls.s32 d16, d16
271 # CHECK: vcls.s8 q8, q8
273 # CHECK: vcls.s16 q8, q8
275 # CHECK: vcls.s32 q8, q8
Dneon.txt269 # CHECK: vcls.s8 d16, d16
271 # CHECK: vcls.s16 d16, d16
273 # CHECK: vcls.s32 d16, d16
275 # CHECK: vcls.s8 q8, q8
277 # CHECK: vcls.s16 q8, q8
279 # CHECK: vcls.s32 q8, q8
/external/vixl/src/aarch32/
Dassembler-aarch32.h4146 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
4147 void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); } in vcls() function
4149 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
4150 void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); } in vcls() function
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc1717 { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */
1720 { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */
1723 { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */
1726 { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */
1729 { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */
1732 { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc1717 { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */
1720 { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */
1723 { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */
1726 { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */
1729 { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */
1732 { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */

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