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Searched refs:vcvt (Results 1 – 25 of 188) sorted by relevance

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/external/llvm-project/llvm/test/MC/ARM/
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dsimple-fp-encoding.s71 vcvt.f32.f64 s0, d16
72 vcvt.f64.f32 d16, s0
74 @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
75 @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
89 vcvt.f64.s32 d16, s0
90 vcvt.f32.s32 s0, s0
91 vcvt.f64.u32 d16, s0
92 vcvt.f32.u32 s0, s0
93 vcvt.s32.f64 s0, d16
94 vcvt.s32.f32 s0, s0
[all …]
Dmve-float.s176 # CHECK: vcvt.f16.s16 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2c]
177 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2c]
178 vcvt.f16.s16 q1, q7, #1
180 # CHECK: vcvt.f16.s16 q1, q7, #16 @ encoding: [0xb0,0xef,0x5e,0x2c]
181 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #16 @ encoding: [0xb0,0xef,0x5e,0x2c]
182 vcvt.f16.s16 q1, q7, #16
184 # CHECK: vcvt.f16.s16 q1, q7, #11 @ encoding: [0xb5,0xef,0x5e,0x2c]
185 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #11 @ encoding: [0xb5,0xef,0x5e,0x2c]
186 vcvt.f16.s16 q1, q7, #11
188 # CHECK: vcvt.s16.f16 q1, q1, #3 @ encoding: [0xbd,0xef,0x52,0x2d]
[all …]
/external/llvm/test/MC/ARM/
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dsimple-fp-encoding.s59 vcvt.f32.f64 s0, d16
60 vcvt.f64.f32 d16, s0
62 @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
63 @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
77 vcvt.f64.s32 d16, s0
78 vcvt.f32.s32 s0, s0
79 vcvt.f64.u32 d16, s0
80 vcvt.f32.u32 s0, s0
81 vcvt.s32.f64 s0, d16
82 vcvt.s32.f32 s0, s0
[all …]
Dfullfp16.s68 vcvt.f16.s32 s0, s0
69 vcvt.f16.u32 s0, s0
70 vcvt.s32.f16 s0, s0
71 vcvt.u32.f16 s0, s0
72 @ ARM: vcvt.f16.s32 s0, s0 @ encoding: [0xc0,0x09,0xb8,0xee]
73 @ ARM: vcvt.f16.u32 s0, s0 @ encoding: [0x40,0x09,0xb8,0xee]
74 @ ARM: vcvt.s32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbd,0xee]
75 @ ARM: vcvt.u32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbc,0xee]
76 @ THUMB: vcvt.f16.s32 s0, s0 @ encoding: [0xb8,0xee,0xc0,0x09]
77 @ THUMB: vcvt.f16.u32 s0, s0 @ encoding: [0xb8,0xee,0x40,0x09]
[all …]
/external/capstone/suite/MC/ARM/
Dneon-convert-encoding.s.cs2 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
3 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16
4 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16
5 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16
6 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8
7 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8
8 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8
9 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8
10 0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1
11 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
[all …]
Dneont2-convert-encoding.s.cs2 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16
3 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16
4 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16
5 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16
6 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8
7 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8
8 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8
9 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8
10 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1
11 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1
[all …]
Dneont2-cmp-encoding.s.cs2 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16
3 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16
4 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16
5 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16
6 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8
7 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8
8 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8
9 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8
10 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1
11 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1
[all …]
Dsimple-fp-encoding.s.cs22 0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16
23 0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0
28 0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0
29 0xc0,0x0a,0xb8,0xee = vcvt.f32.s32 s0, s0
30 0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0
31 0x40,0x0a,0xb8,0xee = vcvt.f32.u32 s0, s0
32 0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16
33 0xc0,0x0a,0xbd,0xee = vcvt.s32.f32 s0, s0
34 0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16
35 0xc0,0x0a,0xbc,0xee = vcvt.u32.f32 s0, s0
[all …]
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-fp.s10 vcvt.f32.f64 s1, d2
11 vcvt.f64.f32 d1, s1
12 vcvt.f32.u16 s1, s2, #8
13 vcvt.f32.s16 s1, s2, #8
14 vcvt.f32.u32 s1, s2, #8
15 vcvt.f32.s32 s1, s2, #8
16 vcvt.u16.f32 s1, s2, #8
17 vcvt.s16.f32 s1, s2, #8
18 vcvt.u32.f32 s1, s2, #8
19 vcvt.s32.f32 s1, s2, #8
[all …]
/external/llvm-project/llvm/test/MC/VE/
DVCVD.s6 # CHECK-INST: vcvt.d.s %v11, %v12
8 vcvt.d.s %v11, %v12
10 # CHECK-INST: vcvt.d.s %v11, %vix, %vm11
12 vcvt.d.s %v11, %vix, %vm11
14 # CHECK-INST: vcvt.d.s %vix, %v22, %vm15
16 vcvt.d.s %vix, %v22, %vm15
18 # CHECK-INST: vcvt.d.s %v63, %v60, %vm2
20 vcvt.d.s %v63, %v60, %vm2
22 # CHECK-INST: vcvt.d.s %vix, %vix
24 vcvt.d.s %vix, %vix, %vm0
[all …]
DVCVS.s6 # CHECK-INST: vcvt.s.d %v11, %v12
8 vcvt.s.d %v11, %v12
10 # CHECK-INST: vcvt.s.d %v11, %vix, %vm11
12 vcvt.s.d %v11, %vix, %vm11
14 # CHECK-INST: vcvt.s.d %vix, %v22, %vm15
16 vcvt.s.d %vix, %v22, %vm15
18 # CHECK-INST: vcvt.s.d %v63, %v60, %vm2
20 vcvt.s.d %v63, %v60, %vm2
22 # CHECK-INST: vcvt.s.d %vix, %vix
24 vcvt.s.d %vix, %vix, %vm0
[all …]
DVFLTX.s6 # CHECK-INST: vcvt.d.l %v11, %v12
8 vcvt.d.l %v11, %v12
10 # CHECK-INST: vcvt.d.l %v11, %vix, %vm11
12 vcvt.d.l %v11, %vix, %vm11
14 # CHECK-INST: vcvt.d.l %vix, %v22, %vm15
16 vcvt.d.l %vix, %v22, %vm15
18 # CHECK-INST: vcvt.d.l %v63, %v60, %vm2
20 vcvt.d.l %v63, %v60, %vm2
22 # CHECK-INST: vcvt.d.l %vix, %vix
24 vcvt.d.l %vix, %vix, %vm0
[all …]
DVFIXX.s6 # CHECK-INST: vcvt.l.d %v11, %v12
8 vcvt.l.d %v11, %v12
10 # CHECK-INST: vcvt.l.d.rz %v11, %vix, %vm11
12 vcvt.l.d.rz %v11, %vix, %vm11
14 # CHECK-INST: vcvt.l.d.rp %vix, %v22, %vm15
16 vcvt.l.d.rp %vix, %v22, %vm15
18 # CHECK-INST: vcvt.l.d.rm %v63, %v60, %vm2
20 vcvt.l.d.rm %v63, %v60, %vm2
22 # CHECK-INST: vcvt.l.d.rn %vix, %vix
24 vcvt.l.d.rn %vix, %vix, %vm0
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvcvt_combine.ll5 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2
9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
15 ; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3
19 %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
20 ret <2 x i32> %vcvt.i
26 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
31 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
32 ret <2 x i32> %vcvt.i
38 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
[all …]
Dfast-isel-conversion.ll11 ; ARM: vcvt.f32.s32 s0, s0
14 ; THUMB: vcvt.f32.s32 s0, s0
26 ; ARM: vcvt.f32.s32 s0, s0
30 ; THUMB: vcvt.f32.s32 s0, s0
42 ; ARM: vcvt.f32.s32 s0, s0
46 ; THUMB: vcvt.f32.s32 s0, s0
57 ; ARM: vcvt.f64.s32 d16, s0
60 ; THUMB: vcvt.f64.s32 d16, s0
72 ; ARM: vcvt.f64.s32 d16, s0
76 ; THUMB: vcvt.f64.s32 d16, s0
[all …]
/external/llvm/test/CodeGen/ARM/
Dvcvt_combine.ll5 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2
9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
15 ; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3
19 %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
20 ret <2 x i32> %vcvt.i
26 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
31 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
32 ret <2 x i32> %vcvt.i
38 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
[all …]
Dfast-isel-conversion.ll11 ; ARM: vcvt.f32.s32 s0, s0
14 ; THUMB: vcvt.f32.s32 s0, s0
26 ; ARM: vcvt.f32.s32 s0, s0
30 ; THUMB: vcvt.f32.s32 s0, s0
42 ; ARM: vcvt.f32.s32 s0, s0
46 ; THUMB: vcvt.f32.s32 s0, s0
57 ; ARM: vcvt.f64.s32 d16, s0
60 ; THUMB: vcvt.f64.s32 d16, s0
72 ; ARM: vcvt.f64.s32 d16, s0
76 ; THUMB: vcvt.f64.s32 d16, s0
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfcvt_combine.ll9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
19 %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
20 ret <4 x i32> %vcvt.i
29 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i64>
30 ret <2 x i64> %vcvt.i
41 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i32>
42 ret <2 x i32> %vcvt.i
52 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i16>
53 ret <2 x i16> %vcvt.i
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfcvt_combine.ll9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
19 %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
20 ret <4 x i32> %vcvt.i
29 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i64>
30 ret <2 x i64> %vcvt.i
41 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i32>
42 ret <2 x i32> %vcvt.i
52 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i16>
53 ret <2 x i16> %vcvt.i
[all …]

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