| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.tbuffer.load.ll | 12 …%vdata = call <4 x i32> @llvm.amdgcn.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32…
16 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
19 …0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
30 …%vdata = call <4 x i32> @llvm.amdgcn.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 4…
31 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
32 ret <4 x float> %vdata.f
41 …%vdata = call <4 x i32> @llvm.amdgcn.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 61, i3…
44 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
47 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
57 …%vdata = call <4 x i32> @llvm.amdgcn.tbuffer.load.v4i32(<4 x i32> %0, i32 %vindex, i32 0, i32 0,…
[all …]
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| D | llvm.amdgcn.struct.tbuffer.load.ll | 18 …%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32…
22 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
25 …0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
38 …%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 42, i32 …
39 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
40 ret <4 x float> %vdata.f
53 …%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 4095, …
56 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
59 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
70 …%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 %vindex, i32 0,…
[all …]
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| D | llvm.amdgcn.raw.tbuffer.load.ll | 17 …%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 78…
21 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
24 …0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
36 …%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 42, i32 0, i32 78,…
37 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
38 ret <4 x float> %vdata.f
50 …%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 4095, i32 61, i3…
53 %vdata.f = bitcast <4 x i32> %vdata to <4 x float>
56 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
67 …%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 %voffs, i32 0, i32…
[all …]
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| D | llvm.amdgcn.tbuffer.load.dwordx3.ll | 9 …%vdata = call <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32> %0, i32 42, i32 0, i32 78,…
10 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
11 ret <3 x float> %vdata.f
21 …%vdata = call <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 42, i32 …
22 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
23 ret <3 x float> %vdata.f
32 …%vdata = call <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 4…
33 %vdata.f = bitcast <3 x i32> %vdata to <3 x float>
34 ret <3 x float> %vdata.f
|
| D | image_ls_mipmap_zero.ll | 64 define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
66 …call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 0, <8 …
73 define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
75 …call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i3…
82 define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 …
84 …call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i3…
91 define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t)…
93 …call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %…
100 define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t,…
102 …call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %…
[all …]
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| D | llvm.amdgcn.tbuffer.store.ll | 32 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 i…
34 %in1 = bitcast <4 x float> %vdata to <4 x i32>
41 define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex) {
43 %in1 = bitcast <4 x float> %vdata to <4 x i32>
50 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
52 %in1 = bitcast <4 x float> %vdata to <4 x i32>
59 define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex, i32 %vof…
61 %in1 = bitcast <4 x float> %vdata to <4 x i32>
74 define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex.1, i32 %v…
76 %in1 = bitcast <4 x float> %vdata to <4 x i32>
|
| D | llvm.amdgcn.struct.tbuffer.store.ll | 42 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 i…
44 %in1 = bitcast <4 x float> %vdata to <4 x i32>
52 define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex) {
54 %in1 = bitcast <4 x float> %vdata to <4 x i32>
62 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
64 %in1 = bitcast <4 x float> %vdata to <4 x i32>
72 define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex, i32 %vof…
74 %in1 = bitcast <4 x float> %vdata to <4 x i32>
89 define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex.1, i32 %v…
91 %in1 = bitcast <4 x float> %vdata to <4 x i32>
|
| /external/arm-optimized-routines/string/aarch64/ |
| D | strrchr-mte.S | 30 #define vdata v1 macro
55 ld1 {vdata.16b}, [src], 16
56 cmeq vhas_nul.16b, vdata.16b, 0
57 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
73 ld1 {vdata.16b}, [src], 16
74 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
75 cmhs vhas_nul.16b, vhas_chr.16b, vdata.16b
80 cmeq vhas_nul.16b, vdata.16b, 0
103 ld1 {vdata.16b}, [src], 16
104 cmeq vhas_nul.16b, vdata.16b, 0
[all …]
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| D | strchrnul-mte.S | 26 #define vdata v1 macro
47 ld1 {vdata.16b}, [src]
50 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
51 cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
67 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
68 cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
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| D | strchr-mte.S | 26 #define vdata v1 macro
49 ld1 {vdata.16b}, [src]
52 cmeq vhas_nul.16b, vdata.16b, 0
53 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
78 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
79 cmhs vhas_nul.16b, vhas_chr.16b, vdata.16b
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| D | strnlen.S | 28 #define vdata v0 macro
50 ld1 {vdata.16b}, [src], 16
52 cmeq vhas_chr.16b, vdata.16b, 0
79 cmeq vhas_chr.16b, vdata.16b, 0
86 cmeq vhas_chr.16b, vdata.16b, 0
|
| D | strlen-mte.S | 26 #define vdata v0 macro
45 ld1 {vdata.16b}, [src]
47 cmeq vhas_nul.16b, vdata.16b, 0
63 cmeq vhas_nul.16b, vdata.16b, 0
|
| D | memrchr.S | 32 #define vdata v1 macro
54 ld1 {vdata.16b}, [src]
58 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
84 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
92 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
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| D | memchr-mte.S | 30 #define vdata v1 macro
51 ld1 {vdata.16b}, [src]
55 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
83 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
91 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
|
| D | strcpy-mte.S | 33 #define vdata v0 macro
62 ld1 {vdata.16b}, [src]
64 cmeq vhas_nul.16b, vdata.16b, 0
73 cmeq vhas_nul.16b, vdata.16b, 0
142 cmeq vhas_nul.16b, vdata.16b, 0
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.SI.tbuffer.store.ll | 7 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
8 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
17 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
18 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
27 %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
28 call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata,
36 define amdgpu_vs void @test4(i32 %vdata, i32 %vaddr) {
37 call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
|
| /external/llvm-project/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_symbolizer_libbacktrace.cpp | 48 static void CplusV3DemangleCallback(const char *s, size_t l, void *vdata) { in CplusV3DemangleCallback() argument
49 CplusV3DemangleData *data = (CplusV3DemangleData *)vdata; in CplusV3DemangleCallback()
109 static int SymbolizeCodePCInfoCallback(void *vdata, uintptr_t addr, in SymbolizeCodePCInfoCallback() argument
112 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodePCInfoCallback()
124 static void SymbolizeCodeCallback(void *vdata, uintptr_t addr, in SymbolizeCodeCallback() argument
126 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodeCallback()
134 static void SymbolizeDataCallback(void *vdata, uintptr_t, const char *symname, in SymbolizeDataCallback() argument
136 DataInfo *info = (DataInfo *)vdata; in SymbolizeDataCallback()
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| /external/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_symbolizer_libbacktrace.cc | 49 static void CplusV3DemangleCallback(const char *s, size_t l, void *vdata) { in CplusV3DemangleCallback() argument
50 CplusV3DemangleData *data = (CplusV3DemangleData *)vdata; in CplusV3DemangleCallback()
109 static int SymbolizeCodePCInfoCallback(void *vdata, uintptr_t addr, in SymbolizeCodePCInfoCallback() argument
112 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodePCInfoCallback()
124 static void SymbolizeCodeCallback(void *vdata, uintptr_t addr, in SymbolizeCodeCallback() argument
126 SymbolizeCodeCallbackArg *cdata = (SymbolizeCodeCallbackArg *)vdata; in SymbolizeCodeCallback()
134 static void SymbolizeDataCallback(void *vdata, uintptr_t, const char *symname, in SymbolizeDataCallback() argument
136 DataInfo *info = (DataInfo *)vdata; in SymbolizeDataCallback()
|
| /external/llvm-project/libc/AOR_v20.02/string/aarch64/ |
| D | strchr-mte.S | 30 #define vdata v1 macro
73 cmeq vhas_nul.16b, vdata.16b, #0
74 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
89 cmeq vhas_nul.16b, vdata.16b, #0
90 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
98 cmeq vhas_nul.16b, vdata.16b, #0
99 cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
|
| /external/skqp/src/opts/ |
| D | SkChecksum_opts.h | 31 /*not static*/ inline uint32_t hash_fn(const void* vdata, size_t bytes, uint32_t seed) { in hash_fn() argument
32 auto data = (const uint8_t*)vdata; in hash_fn()
87 /*not static*/ inline uint32_t hash_fn(const void* vdata, size_t bytes, uint32_t hash) { in hash_fn() argument
88 auto data = (const uint8_t*)vdata; in hash_fn()
131 /*not static*/ inline uint32_t hash_fn(const void* vdata, size_t bytes, uint32_t hash) { in hash_fn() argument
132 auto data = (const uint8_t*)vdata; in hash_fn()
176 /*not static*/ inline uint32_t hash_fn(const void* vdata, size_t bytes, uint32_t hash) { in hash_fn() argument
177 auto data = (const uint8_t*)vdata; in hash_fn()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 41 …pu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
42 …pu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
45 …ds_add_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amd…
46 …ds_add_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amd…
47 …ds_and_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amd…
48 …ds_and_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amd…
49 …pu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
50 …pu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
62 …pu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
64 …pu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdat…
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 28 // vdata/vaddr size.
226 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
231 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
238 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
250 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
320 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
324 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
332 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
[all …]
|
| /external/rust/crates/grpcio-sys/grpc/src/core/lib/slice/ |
| D | b64.cc | 59 char* grpc_base64_encode(const void* vdata, size_t data_size, int url_safe, in grpc_base64_encode() argument
64 grpc_base64_encode_core(result, vdata, data_size, url_safe, multiline); in grpc_base64_encode()
77 void grpc_base64_encode_core(char* result, const void* vdata, size_t data_size, in grpc_base64_encode_core() argument
79 const unsigned char* data = static_cast<const unsigned char*>(vdata); in grpc_base64_encode_core()
|
| /external/grpc-grpc/src/core/lib/slice/ |
| D | b64.cc | 59 char* grpc_base64_encode(const void* vdata, size_t data_size, int url_safe, in grpc_base64_encode() argument
64 grpc_base64_encode_core(result, vdata, data_size, url_safe, multiline); in grpc_base64_encode()
78 void grpc_base64_encode_core(char* result, const void* vdata, size_t data_size, in grpc_base64_encode_core() argument
80 const unsigned char* data = static_cast<const unsigned char*>(vdata); in grpc_base64_encode_core()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 28 // vdata/vaddr size.
242 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
247 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
254 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
259 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
266 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
272 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
336 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
340 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
348 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
[all …]
|